From f30716767fcb6362e5278181798b8cb653600cff Mon Sep 17 00:00:00 2001 From: Jaby Date: Wed, 7 Sep 2022 19:47:56 +0200 Subject: [PATCH 1/2] Small cleanup of boot related sources --- lib/pcsx-redux/ps-exe.ld | 18 +++++++++--------- .../BootLoader/{boot_spu.cpp => spu_boot.cpp} | 0 .../{boot_start.cpp => start_boot.cpp} | 0 3 files changed, 9 insertions(+), 9 deletions(-) rename src/Library/src/BootLoader/{boot_spu.cpp => spu_boot.cpp} (100%) rename src/Library/src/BootLoader/{boot_start.cpp => start_boot.cpp} (100%) diff --git a/lib/pcsx-redux/ps-exe.ld b/lib/pcsx-redux/ps-exe.ld index a91afff1..cff77471 100644 --- a/lib/pcsx-redux/ps-exe.ld +++ b/lib/pcsx-redux/ps-exe.ld @@ -68,16 +68,16 @@ SECTIONS { { .planschi { - *libJabyEngine.a:boot_*.o(.text.startup._GLOBAL__*) - *libJabyEngine.a:boot_*.o(.ctors) + *libJabyEngine.a:*_boot.o(.text.startup._GLOBAL__*) + *libJabyEngine.a:*_boot.o(.ctors) - *libJabyEngine.a:boot_*.o(.text.*) - *libJabyEngine.a:boot_*.o(.rodata*) - *libJabyEngine.a:boot_*.o(.sdata*) - *libJabyEngine.a::boot_*.o(.data*) - *libJabyEngine.a::boot_*.o(.sbss*) - *libJabyEngine.a::boot_*.o(.bss*) - *libJabyEngine.a::boot_*.o(*) + *libJabyEngine.a:*_boot.o(.text.*) + *libJabyEngine.a:*_boot.o(.rodata*) + *libJabyEngine.a:*_boot.o(.sdata*) + *libJabyEngine.a::*_boot.o(.data*) + *libJabyEngine.a::*_boot.o(.sbss*) + *libJabyEngine.a::*_boot.o(.bss*) + *libJabyEngine.a::*_boot.o(*) } } __boot_loader_end = .; diff --git a/src/Library/src/BootLoader/boot_spu.cpp b/src/Library/src/BootLoader/spu_boot.cpp similarity index 100% rename from src/Library/src/BootLoader/boot_spu.cpp rename to src/Library/src/BootLoader/spu_boot.cpp diff --git a/src/Library/src/BootLoader/boot_start.cpp b/src/Library/src/BootLoader/start_boot.cpp similarity index 100% rename from src/Library/src/BootLoader/boot_start.cpp rename to src/Library/src/BootLoader/start_boot.cpp From 27716c020c10253a124aee96fd99433ac3a00b66 Mon Sep 17 00:00:00 2001 From: Jaby Date: Wed, 7 Sep 2022 19:49:37 +0200 Subject: [PATCH 2/2] Add Port namespace for DMA --- include/PSX/System/IOPorts/DMA_IO.hpp | 226 ++++++++++++------------ src/Library/src/BootLoader/spu_boot.cpp | 2 +- 2 files changed, 115 insertions(+), 113 deletions(-) diff --git a/include/PSX/System/IOPorts/DMA_IO.hpp b/include/PSX/System/IOPorts/DMA_IO.hpp index b93961d7..dec0cf13 100644 --- a/include/PSX/System/IOPorts/DMA_IO.hpp +++ b/include/PSX/System/IOPorts/DMA_IO.hpp @@ -3,140 +3,142 @@ #include "IOPort.hpp" namespace DMA { - struct __no_align MADR : public ComplexBitMap { - __io_port_inherit_complex_bit_map(MADR); + namespace Port { + struct __no_align MADR : public ComplexBitMap { + __io_port_inherit_complex_bit_map(MADR); - static constexpr BitRange MemoryAdr = BitRange::from_to(0, 23); - }; - - struct __no_align BCR : public ComplexBitMap { - __io_port_inherit_complex_bit_map(BCR); - - struct __no_align SyncMode0 { - static constexpr BitRange NumberOfWords = BitRange::from_to(0, 15); - static constexpr Bit CD_OneBlock = 16; + static constexpr BitRange MemoryAdr = BitRange::from_to(0, 23); }; - struct __no_align SyncMode1 { - static constexpr BitRange BlockSize = BitRange::from_to(0, 15); - static constexpr BitRange BlockAmount = BitRange::from_to(16, 31); + struct __no_align BCR : public ComplexBitMap { + __io_port_inherit_complex_bit_map(BCR); + + struct __no_align SyncMode0 { + static constexpr BitRange NumberOfWords = BitRange::from_to(0, 15); + static constexpr Bit CD_OneBlock = 16; + }; + + struct __no_align SyncMode1 { + static constexpr BitRange BlockSize = BitRange::from_to(0, 15); + static constexpr BitRange BlockAmount = BitRange::from_to(16, 31); + }; + + struct __no_align SyncMode2 { + }; }; - struct __no_align SyncMode2 { - }; - }; + struct __no_align CHCHR : public ComplexBitMap { + __io_port_inherit_complex_bit_map(CHCHR); - struct __no_align CHCHR : public ComplexBitMap { - __io_port_inherit_complex_bit_map(CHCHR); + enum _SyncMode { + Sync0 = 0, //Start immediately, + Sync1 = 1, //Sync blocks to DMA requests + Sync2 = 2, //Linked List + }; - enum _SyncMode { - Sync0 = 0, //Start immediately, - Sync1 = 1, //Sync blocks to DMA requests - Sync2 = 2, //Linked List + static constexpr Bit ManualStart = 28; + + static constexpr Bit Start = 24; + static constexpr auto Busy = Start; + + static constexpr BitRange ChoppingCPUWindowSize = BitRange::from_to(20, 22); + static constexpr BitRange ChoppingDMAWindowSize = BitRange::from_to(16, 18); + + static constexpr BitRange<_SyncMode> SyncMode = BitRange<_SyncMode>::from_to(9, 10); + static constexpr auto UseSyncMode0 = (SyncMode << Sync0); + static constexpr auto UseSyncMode1 = (SyncMode << Sync1); + static constexpr auto UseSyncMode2 = (SyncMode << Sync2); + + static constexpr Bit UseChopping = 8; + + static constexpr Bit MemoryAdrDecreaseBy4 = 1; + static constexpr auto MemoryAdrIncreaseBy4 = !MemoryAdrDecreaseBy4; + + static constexpr Bit FromMainRAM = 0; + static constexpr auto ToMainRAM = !FromMainRAM; + + static constexpr CHCHR StartMDECin() { + return CHCHR(0x01000201); + } + + static constexpr CHCHR StartMDECout() { + return CHCHR(0x01000200); + } + + static constexpr CHCHR StartGPUReceive() { + return CHCHR(0x01000201); + } + + static constexpr CHCHR StartCDROM() { + return CHCHR(0x11000000); + } + + static constexpr CHCHR StartSPUReceive() { + return CHCHR(0x01000201); + } + + static constexpr CHCHR StartOTC() { + return CHCHR(0x11000002); + } }; - static constexpr Bit ManualStart = 28; + struct __no_align Registers { + MADR adr; + BCR block_ctrl; + CHCHR channel_ctrl; + }; - static constexpr Bit Start = 24; - static constexpr auto Busy = Start; + //0: Highest, 7: Lowest + typedef uint32_t Priority; + static constexpr Priority HighestPriority = 0; + static constexpr Priority LowestPriority = 7; - static constexpr BitRange ChoppingCPUWindowSize = BitRange::from_to(20, 22); - static constexpr BitRange ChoppingDMAWindowSize = BitRange::from_to(16, 18); + struct __no_align DMAControlRegister : public ComplexBitMap { + __io_port_inherit_complex_bit_map(DMAControlRegister); - static constexpr BitRange<_SyncMode> SyncMode = BitRange<_SyncMode>::from_to(9, 10); - static constexpr auto UseSyncMode0 = (SyncMode << Sync0); - static constexpr auto UseSyncMode1 = (SyncMode << Sync1); - static constexpr auto UseSyncMode2 = (SyncMode << Sync2); + static constexpr Bit OTCEnable = 27; + static constexpr BitRange OTCPriority = BitRange::from_to(24, 26); - static constexpr Bit UseChopping = 8; + static constexpr Bit PIOEnable = 23; + static constexpr BitRange PIOPriority = BitRange::from_to(20, 22); - static constexpr Bit MemoryAdrDecreaseBy4 = 1; - static constexpr auto MemoryAdrIncreaseBy4 = !MemoryAdrDecreaseBy4; + static constexpr Bit SPUEnable = 19; + static constexpr BitRange SPUPriority = BitRange::from_to(16, 18); - static constexpr Bit FromMainRAM = 0; - static constexpr auto ToMainRAM = !FromMainRAM; + static constexpr Bit CDROMEnable = 15; + static constexpr BitRange CDROMPriority = BitRange::from_to(12, 14); - static constexpr CHCHR StartMDECin() { - return CHCHR(0x01000201); - } + static constexpr Bit GPUEnable = 11; + static constexpr BitRange GPUPriority = BitRange::from_to(8, 10); - static constexpr CHCHR StartMDECout() { - return CHCHR(0x01000200); - } + static constexpr Bit MDECoutEnable = 7; + static constexpr BitRange MDECoutPriority = BitRange::from_to(4, 6); - static constexpr CHCHR StartGPUReceive() { - return CHCHR(0x01000201); - } + static constexpr Bit MDECinEnable = 3; + static constexpr BitRange MDECinPriority = BitRange::from_to(0, 2); + }; - static constexpr CHCHR StartCDROM() { - return CHCHR(0x11000000); - } + struct __no_align DMAInterruptRegister : public ComplexBitMap { + __io_port_inherit_complex_bit_map(DMAInterruptRegister); - static constexpr CHCHR StartSPUReceive() { - return CHCHR(0x01000201); - } + static constexpr Bit MasterEnable = 31; + static constexpr BitRange Flags = BitRange::from_to(24, 30); + static constexpr Bit MasterEnableDPCR = 23; + static constexpr BitRange EnableDPCR = BitRange::from_to(16, 22); + static constexpr Bit ForceIRQ = 15; + }; - static constexpr CHCHR StartOTC() { - return CHCHR(0x11000002); - } - }; + __declare_io_port_global(Registers, MDECin, 0x1F801080); + __declare_io_port_global(Registers, MDECout, 0x1F801090); + __declare_io_port_global(Registers, GPU, 0x1F8010A0); + __declare_io_port_global(Registers, CDROM, 0x1F8010B0); + __declare_io_port_global(Registers, SPU, 0x1F8010C0); + __declare_io_port_global(Registers, PIO, 0x1F8010D0); + __declare_io_port_global(Registers, OTC, 0x1F8010E0); - struct __no_align Registers { - MADR adr; - BCR block_ctrl; - CHCHR channel_ctrl; - }; - - //0: Highest, 7: Lowest - typedef uint32_t Priority; - static constexpr Priority HighestPriority = 0; - static constexpr Priority LowestPriority = 7; - - struct __no_align DMAControlRegister : public ComplexBitMap { - __io_port_inherit_complex_bit_map(DMAControlRegister); - - static constexpr Bit OTCEnable = 27; - static constexpr BitRange OTCPriority = BitRange::from_to(24, 26); - - static constexpr Bit PIOEnable = 23; - static constexpr BitRange PIOPriority = BitRange::from_to(20, 22); - - static constexpr Bit SPUEnable = 19; - static constexpr BitRange SPUPriority = BitRange::from_to(16, 18); - - static constexpr Bit CDROMEnable = 15; - static constexpr BitRange CDROMPriority = BitRange::from_to(12, 14); - - static constexpr Bit GPUEnable = 11; - static constexpr BitRange GPUPriority = BitRange::from_to(8, 10); - - static constexpr Bit MDECoutEnable = 7; - static constexpr BitRange MDECoutPriority = BitRange::from_to(4, 6); - - static constexpr Bit MDECinEnable = 3; - static constexpr BitRange MDECinPriority = BitRange::from_to(0, 2); - }; - - struct __no_align DMAInterruptRegister : public ComplexBitMap { - __io_port_inherit_complex_bit_map(DMAInterruptRegister); - - static constexpr Bit MasterEnable = 31; - static constexpr BitRange Flags = BitRange::from_to(24, 30); - static constexpr Bit MasterEnableDPCR = 23; - static constexpr BitRange EnableDPCR = BitRange::from_to(16, 22); - static constexpr Bit ForceIRQ = 15; - }; - - __declare_io_port_global(Registers, MDECin, 0x1F801080); - __declare_io_port_global(Registers, MDECout, 0x1F801090); - __declare_io_port_global(Registers, GPU, 0x1F8010A0); - __declare_io_port_global(Registers, CDROM, 0x1F8010B0); - __declare_io_port_global(Registers, SPU, 0x1F8010C0); - __declare_io_port_global(Registers, PIO, 0x1F8010D0); - __declare_io_port_global(Registers, OTC, 0x1F8010E0); - - __declare_io_port_global(DMAControlRegister, DPCR, 0x1F8010F0); - __declare_io_port_global(DMAInterruptRegister, DICR, 0x1F8010F4); + __declare_io_port_global(DMAControlRegister, DPCR, 0x1F8010F0); + __declare_io_port_global(DMAInterruptRegister, DICR, 0x1F8010F4); + } } #endif //!__JABYENGINE_DMA_IO_HPP__ \ No newline at end of file diff --git a/src/Library/src/BootLoader/spu_boot.cpp b/src/Library/src/BootLoader/spu_boot.cpp index 8505efcd..9446b243 100644 --- a/src/Library/src/BootLoader/spu_boot.cpp +++ b/src/Library/src/BootLoader/spu_boot.cpp @@ -3,7 +3,7 @@ namespace SPU { using namespace Port; - using namespace DMA; + using namespace DMA::Port; static void clear_key() { Key::off.write(UI32_MAX);