diff --git a/include/PSX/System/IOPorts/dma_io.hpp b/include/PSX/System/IOPorts/dma_io.hpp index 2e747ede..4c016add 100644 --- a/include/PSX/System/IOPorts/dma_io.hpp +++ b/include/PSX/System/IOPorts/dma_io.hpp @@ -4,18 +4,18 @@ namespace JabyEngine { namespace DMA_IO { - __declare_io_type(MADR, uint32_t, + __new_declare_io_value(MADR, uint32_t) { static constexpr auto MemoryAdr = BitRange::from_to(0, 23); - ); + }; - __declare_io_type(BCR, uint32_t, + __new_declare_io_value(BCR, uint32_t) { struct SyncMode0 { static constexpr auto NumberOfWords = BitRange::from_to(0, 15); static constexpr auto CD_OneBlock = Bit(16); - static constexpr Self for_cd() { - // v Should be replaced with a named constant - return Self::from(SyncMode0::CD_OneBlock, SyncMode0::NumberOfWords.with(512)); + static constexpr BCR for_cd() { + // v Should be replaced with a named constant + return BCR::from(SyncMode0::CD_OneBlock, SyncMode0::NumberOfWords.with(512)); } }; @@ -25,10 +25,13 @@ namespace JabyEngine { }; struct SyncMode2 { + static constexpr BCR for_gpu_cmd() { + return {0}; + } }; - ); + }; - __declare_io_type(CHCHR, uint32_t, + __new_declare_io_value(CHCHR, uint32_t) { enum SyncMode_t { Sync0 = 0, //Start immediately, Sync1 = 1, //Sync blocks to DMA requests @@ -56,66 +59,57 @@ namespace JabyEngine { static constexpr auto FromMainRAM = Bit(0); static constexpr auto ToMainRAM = !FromMainRAM; - static constexpr Self StartMDECin() { - return Self{0x01000201}; + static constexpr CHCHR StartMDECin() { + return CHCHR{0x01000201}; } - static constexpr Self StartMDECout() { - return Self{0x01000200}; + static constexpr CHCHR StartMDECout() { + return CHCHR{0x01000200}; } - static constexpr Self StartGPUReceive() { - return Self{0x01000201}; + static constexpr CHCHR StartGPUReceive() { + return CHCHR{0x01000201}; } - static constexpr Self StartGPULinked() { - return Self{0x01000401}; + static constexpr CHCHR StartGPULinked() { + return CHCHR{0x01000401}; } - static constexpr Self StartCDROM() { - return Self{0x11000000}; + static constexpr CHCHR StartCDROM() { + return CHCHR{0x11000000}; } - static constexpr Self StartSPUReceive() { - return Self{0x01000201}; + static constexpr CHCHR StartSPUReceive() { + return CHCHR{0x01000201}; } - static constexpr Self StartOTC() { - return Self{0x11000002}; + static constexpr CHCHR StartOTC() { + return CHCHR{0x11000002}; } - ); + }; #pragma pack(push, 1) struct Registers { - MADR_v adr; - BCR_v block_ctrl; - CHCHR_v channel_ctrl; + New::IOPort adr; + New::IOPort block_ctrl; + New::IOPort channel_ctrl; void set_adr(uintptr_t adr) { - this->adr.set(MADR_t::MemoryAdr.with(adr)); + this->adr.write({bit::value::set_normalized(0u, MADR::MemoryAdr.with(adr))}); } void wait() { - while(this->channel_ctrl.is_set(CHCHR_t::Busy)); + while(this->channel_ctrl.read().is_set2(CHCHR::Busy)); } }; #pragma pack(pop) - // Those types do not need to be volatile because there members are - typedef Registers MDECin_v; - typedef Registers MDECout_v; - typedef Registers GPU_v; - typedef Registers CDROM_v; - typedef Registers SPU_v; - typedef Registers PIO_v; - typedef Registers OTC_v; - //0: Highest, 7: Lowest typedef uint32_t Priority; static constexpr Priority HighestPriority = 0; static constexpr Priority LowestPriority = 7; - __declare_io_type(DPCR, uint32_t, + __new_declare_io_value(DPCR, uint32_t) { static constexpr auto OTCEnable = Bit(27); static constexpr auto OTCPriority = BitRange::from_to(24, 26); @@ -136,26 +130,26 @@ namespace JabyEngine { static constexpr auto MDECinEnable = Bit(3); static constexpr auto MDECinPriority = BitRange::from_to(0, 2); - ); + }; - __declare_io_type(DICR, uint32_t, + __new_declare_io_value(DICR, uint32_t) { static constexpr auto MasterEnable = Bit(31); static constexpr auto Flags = BitRange::from_to(24, 30); static constexpr auto MasterEnableDPCR = Bit(23); static constexpr auto EnableDPCR = BitRange::from_to(16, 22); static constexpr auto ForceIRQ = Bit(15); - ); + }; - __declare_new_io_port(MDECin, 0x1F801080); - __declare_new_io_port(MDECout, 0x1F801090); - __declare_new_io_port(GPU, 0x1F8010A0); - __declare_new_io_port(CDROM, 0x1F8010B0); - __declare_new_io_port(SPU, 0x1F8010C0); - __declare_new_io_port(PIO, 0x1F8010D0); - __declare_new_io_port(OTC, 0x1F8010E0); + __new_declare_value_at(Registers, MDECin, 0x1F801080); + __new_declare_value_at(Registers, MDECout, 0x1F801090); + __new_declare_value_at(Registers, GPU, 0x1F8010A0); + __new_declare_value_at(Registers, CDROM, 0x1F8010B0); + __new_declare_value_at(Registers, SPU, 0x1F8010C0); + __new_declare_value_at(Registers, PIO, 0x1F8010D0); + __new_declare_value_at(Registers, OTC, 0x1F8010E0); - __declare_new_io_port(DPCR, 0x1F8010F0); - __declare_new_io_port(DICR, 0x1F8010F4); + __new_declare_io_port(DPCR, 0x1F8010F0); + __new_declare_io_port(DICR, 0x1F8010F4); } } #endif //!__JABYENGINE_DMA_IO_HPP__ \ No newline at end of file diff --git a/include/PSX/System/IOPorts/ioport.hpp b/include/PSX/System/IOPorts/ioport.hpp index f013cebe..3ad0cf86 100644 --- a/include/PSX/System/IOPorts/ioport.hpp +++ b/include/PSX/System/IOPorts/ioport.hpp @@ -24,20 +24,31 @@ namespace JabyEngine { constexpr T& set2(ClearBit bit) { this->raw = bit::set(this->raw, bit); - return *this; + return static_cast(*this); } constexpr T& set2(BitRange bits, T value) { this->raw = bit::value::set_normalized(this->raw, bits, value); - return *this; + return static_cast(*this); } template constexpr T& set2(const BitRange::RangeValuePair& value) { this->raw = bit::value::set_normalized(this->raw, value); - return *this; + return static_cast(*this); + } + + template + constexpr T& set2(const U& first) { + return IOValue::set2(first); } + template + constexpr T& set2(const U& first, const ARGS& ...args) { + IOValue::set2(first); + return IOValue::set2(args...); + } + template constexpr T& set_va(const U& head) { return this->set2(head); @@ -108,8 +119,9 @@ namespace JabyEngine { }; #define __new_declare_io_value(name, type) struct name : public ::JabyEngine::New::internal::IOValue - #define __new_declare_io_port_w_type(type, name, adr) static auto& name = *reinterpret_cast<::JabyEngine::New::IOPort*>(IOAdress::patch_adr(adr)) - #define __new_declare_io_port(name, adr) __new_declare_io_port_w_type(name, name, adr) + #define __new_declare_value_at(type, name, adr) static auto& name = *reinterpret_cast(IOAdress::patch_adr(adr)) + #define __new_declare_io_port_w_type(type, name, adr) __new_declare_value_at(::JabyEngine::New::IOPort, name, adr) + #define __new_declare_io_port(name, adr) __new_declare_io_port_w_type(struct name, name, adr) } namespace IOPort { diff --git a/src/Library/internal-include/GPU/gpu_internal.hpp b/src/Library/internal-include/GPU/gpu_internal.hpp index 891abf77..d29bee85 100644 --- a/src/Library/internal-include/GPU/gpu_internal.hpp +++ b/src/Library/internal-include/GPU/gpu_internal.hpp @@ -91,10 +91,10 @@ namespace JabyEngine { } static void start(uint16_t blockCount, uint16_t wordsPerBlock = 0x10) { - typedef DMA_IO::BCR_t::SyncMode1 SyncMode1; + typedef DMA_IO::BCR::SyncMode1 SyncMode1; - DMA_IO::GPU.block_ctrl = DMA_IO::BCR_t::from(SyncMode1::BlockSize.with(wordsPerBlock), SyncMode1::BlockAmount.with(blockCount)); - DMA_IO::GPU.channel_ctrl = DMA_IO::CHCHR_t::StartGPUReceive(); + DMA_IO::GPU.block_ctrl.write(DMA_IO::BCR::from(SyncMode1::BlockSize.with(wordsPerBlock), SyncMode1::BlockAmount.with(blockCount))); + DMA_IO::GPU.channel_ctrl.write(DMA_IO::CHCHR::StartGPUReceive()); } } } diff --git a/src/Library/src/BootLoader/start_boot.cpp b/src/Library/src/BootLoader/start_boot.cpp index 4fea533c..c086c7d1 100644 --- a/src/Library/src/BootLoader/start_boot.cpp +++ b/src/Library/src/BootLoader/start_boot.cpp @@ -31,7 +31,10 @@ namespace JabyEngine { namespace Start { static void enable_DMA() { ::JabyEngine::Blubb::bla(::JabyEngine::Blubb::Test); - DMA_IO::DPCR = DMA_IO::DPCR_t(DMA_IO::DPCR).set(DMA_IO::DPCR_t::SPUEnable).set(DMA_IO::DPCR_t::GPUEnable).set(DMA_IO::DPCR_t::CDROMEnable); + + asm("#miau"); + DMA_IO::DPCR.write(DMA_IO::DPCR.read().set2(DMA_IO::DPCR::SPUEnable, DMA_IO::DPCR::GPUEnable, DMA_IO::DPCR::CDROMEnable)); + asm("#miau"); } static void setup() { diff --git a/src/Library/src/CD/cd.cpp b/src/Library/src/CD/cd.cpp index d5ff40c5..7a95d5ce 100644 --- a/src/Library/src/CD/cd.cpp +++ b/src/Library/src/CD/cd.cpp @@ -45,8 +45,8 @@ namespace JabyEngine { static const auto ReadSector = [](uint32_t* dst) { DMA_IO::CDROM.set_adr(reinterpret_cast(dst)); - DMA_IO::CDROM.block_ctrl = DMA_IO::BCR_t::SyncMode0::for_cd(); - DMA_IO::CDROM.channel_ctrl = DMA_IO::CHCHR_t::StartCDROM(); + DMA_IO::CDROM.block_ctrl.write(DMA_IO::BCR::SyncMode0::for_cd()); + DMA_IO::CDROM.channel_ctrl.write(DMA_IO::CHCHR::StartCDROM()); DMA_IO::CDROM.wait(); diff --git a/src/Library/src/GPU/gpu.cpp b/src/Library/src/GPU/gpu.cpp index 8d1a6a24..897de61c 100644 --- a/src/Library/src/GPU/gpu.cpp +++ b/src/Library/src/GPU/gpu.cpp @@ -68,8 +68,8 @@ namespace JabyEngine { // DPCR already enabled GPU_IO::GP1 = GPU_IO::Command::DMADirection(GPU_IO::DMADirection::CPU2GPU); DMA_IO::GPU.set_adr(reinterpret_cast(data)); - DMA_IO::GPU.block_ctrl = 0; - DMA_IO::GPU.channel_ctrl = DMA_IO::CHCHR_t::StartGPULinked(); + DMA_IO::GPU.block_ctrl.write(DMA_IO::BCR::SyncMode2::for_gpu_cmd()); + DMA_IO::GPU.channel_ctrl.write(DMA_IO::CHCHR::StartGPULinked()); } }