#ifndef __JABYENGINE_INTERRUPT_IO_HPP__
#define __JABYENGINE_INTERRUPT_IO_HPP__
#include "ioport.hpp"

namespace JabyEngine {
    namespace Interrupt {
        static constexpr auto VBlank     = Bit<uint32_t>(0);
        static constexpr auto GPU        = Bit<uint32_t>(1);
        static constexpr auto CDROM      = Bit<uint32_t>(2);
        static constexpr auto DMA        = Bit<uint32_t>(3);
        static constexpr auto Timer0     = Bit<uint32_t>(4);
        static constexpr auto Timer1     = Bit<uint32_t>(5);
        static constexpr auto Timer2     = Bit<uint32_t>(6);
        static constexpr auto Periphery  = Bit<uint32_t>(7);
        static constexpr auto SIO        = Bit<uint32_t>(8);
        static constexpr auto SPU        = Bit<uint32_t>(9);
        static constexpr auto Controller = Bit<uint32_t>(10);
        static constexpr auto LightPen   = Controller;
        
        struct __no_align IRQStatus : public ComplexBitMap<uint32_t> {
            __io_port_inherit_complex_bit_map(IRQStatus);
        };

        struct __no_align IRQMask   : public ComplexBitMap<uint32_t> {
            __io_port_inherit_complex_bit_map(IRQMask);
        };

        __declare_io_port_global(IRQStatus, Status, 0x1F801070);
        __declare_io_port_global(IRQMask,   Mask,   0x1F801074);

        static bool is_irq(Bit<uint32_t> irq) {
            return Status.read().is_bit_set(irq);
        }

        static void ack_irg(Bit<uint32_t> irq) {
            Status.write(Status.read().clear_bit(irq));
        }

        static void disable_irq(Bit<uint32_t> irq) {
            Mask.write(Mask.read().clear_bit(irq));
        }

        static void enable_irq(Bit<uint32_t> irq) {
            Mask.write(Mask.read().set_bit(irq));
        }
    }
}

#endif //!__JABYENGINE_INTERRUPT_IO_HPP__