#ifndef __JABYENGINE_INTERNAL_GPU_HPP__
#define __JABYENGINE_INTERNAL_GPU_HPP__
#include <PSX/GPU/GPU_Types.hpp>
#include <PSX/System/IOPorts/DMA_IO.hpp>
#include <PSX/System/IOPorts/GPU_IO.hpp>

namespace GPU {
    struct DisplayMode {
        enum struct TVEncoding {
            NTSC = 0,
            PAL  = 1,
        };

        static constexpr auto HorizontalResolution368 = Bit<uint32_t>(6);
        static constexpr auto VerticalInterlace       = Bit<uint32_t>(5);
        static constexpr auto DisplayAreaColorDepth   = BitRange<GPU::DisplayAreaColorDepth>::from_to(4, 4);
        static constexpr auto VideoMode               = BitRange<TVEncoding>::from_to(3, 3);
        static constexpr auto VerticalResolution      = BitRange<GPU::VerticalResolution>::from_to(2, 2);
        static constexpr auto HorizontalResolution    = BitRange<GPU::HorizontalResolution>::from_to(0, 1);

        static constexpr uint32_t PAL() {
            return ComplexBitMap<uint32_t>::with(
                DisplayMode::HorizontalResolution.with(GPU::HorizontalResolution::$320),
                DisplayMode::VerticalResolution.with(GPU::VerticalResolution::$240),
                DisplayMode::VideoMode.with(TVEncoding::PAL),
                DisplayMode::DisplayAreaColorDepth.with(GPU::DisplayAreaColorDepth::$15bit)
            ).raw;
        }
    };

    static void quick_fill_fast(const Color24& color, const PositionU16& pos, const SizeU16& size) {
        GP0.write(Command::GP0::QuickFill(color));
        GP0.write(Command::GP0::TopLeftPosition(pos.x, pos.y));
        GP0.write(Command::GP0::WidthHeight(size.width, size.height));
    }

    static void reset_cmd_buffer() {
        GP1.write(Command::GP1::ResetCMDBufer());
    }

    static void wait_ready_for_CMD() {
        while(!GPUSTAT.ref().is(GPUStatusRegister::GP0ReadyForCMD));
    }

    namespace DMA {
        static void wait() {
            while(::DMA::GPU.channel_ctrl.ref().is(::DMA::CHCHR::Busy));
        }

        static void end() {
            reset_cmd_buffer();
        }

        namespace Receive {
            static void prepare()
            {
                GP1.write(Command::GP1::DMADirection(DMADirection::CPU2GPU));
                reset_cmd_buffer();
            }

            static void set_src(uintptr_t adr) {
                ::DMA::GPU.adr.ref().set_value(static_cast<uint32_t>(adr), ::DMA::MADR::MemoryAdr);
            }

            static void set_dst(const PositionU16& position, const SizeU16& size) {

                wait_ready_for_CMD();
                GP0.write(Command::GP0::CPU2VRAM_Blitting());
                GP0.write(Command::GP0::TopLeftPosition(position.x, position.y));
                GP0.write(Command::GP0::WidthHeight(size.width, size.height));
            }

            static void start(uint16_t blockCount, uint16_t wordsPerBlock = 0x10) {
                typedef ::DMA::BCR::SyncMode1 SyncMode1;

                ::DMA::GPU.block_ctrl.write(SyncMode1::with(SyncMode1::BlockSize.with(wordsPerBlock), SyncMode1::BlockAmount.with(blockCount)));
                ::DMA::GPU.channel_ctrl.write(::DMA::CHCHR::StartGPUReceive());
            }
        }
    }
}

#endif //!__JABYENGINE_INTERNAL_GPU_HPP__