#ifndef __JABYENGINE_DMA_IO_HPP__
#define __JABYENGINE_DMA_IO_HPP__
#include "IOPort.hpp"

namespace DMA {
    namespace Port {
        struct __no_align MADR : public ComplexBitMap<uint32_t> {
            __io_port_inherit_complex_bit_map(MADR);

            static constexpr auto MemoryAdr = BitRange<uint32_t>::from_to(0, 23);
        };

        struct __no_align BCR : public ComplexBitMap<uint32_t> {
            __io_port_inherit_complex_bit_map(BCR);

            struct __no_align SyncMode0 {
                static constexpr auto NumberOfWords = BitRange<uint16_t>::from_to(0, 15);
                static constexpr auto CD_OneBlock   = Bit<uint16_t>(16);
            };

            struct __no_align SyncMode1 {
                static constexpr auto BlockSize   = BitRange<uint16_t>::from_to(0, 15);
                static constexpr auto BlockAmount = BitRange<uint16_t>::from_to(16, 31);
            };

            struct __no_align SyncMode2 {
            };
        };

        struct __no_align CHCHR : public ComplexBitMap<uint32_t> {
            __io_port_inherit_complex_bit_map(CHCHR);

            enum _SyncMode {
                Sync0 = 0, //Start immediately,
                Sync1 = 1, //Sync blocks to DMA requests
                Sync2 = 2, //Linked List
            };

            static constexpr auto ManualStart = Bit<uint32_t>(28);

            static constexpr auto Start = Bit<uint32_t>(24);
            static constexpr auto Busy  = Start;

            static constexpr auto ChoppingCPUWindowSize = BitRange<uint32_t>::from_to(20, 22);
            static constexpr auto ChoppingDMAWindowSize = BitRange<uint32_t>::from_to(16, 18);

            static constexpr auto SyncMode     = BitRange<_SyncMode>::from_to(9, 10);
            static constexpr auto UseSyncMode0 = SyncMode.with(Sync0);
            static constexpr auto UseSyncMode1 = SyncMode.with(Sync1);
            static constexpr auto UseSyncMode2 = SyncMode.with(Sync2);

            static constexpr auto UseChopping   = Bit<uint32_t>(8);

            static constexpr auto MemoryAdrDecreaseBy4 = Bit<uint32_t>(1);
            static constexpr auto MemoryAdrIncreaseBy4 = !MemoryAdrDecreaseBy4;

            static constexpr auto FromMainRAM = Bit<uint32_t>(0);
            static constexpr auto ToMainRAM   = !FromMainRAM;

            static constexpr CHCHR StartMDECin() {
                return CHCHR(0x01000201);
            }

            static constexpr CHCHR StartMDECout() {
                return CHCHR(0x01000200);
            }

            static constexpr CHCHR StartGPUReceive() {
                return CHCHR(0x01000201);
            }

            static constexpr CHCHR StartCDROM() {
                return CHCHR(0x11000000);
            }

            static constexpr CHCHR StartSPUReceive() {
                return CHCHR(0x01000201);
            }

            static constexpr CHCHR StartOTC() {
                return CHCHR(0x11000002);
            }
        };

        struct __no_align Registers {
            MADR  adr;
            BCR   block_ctrl;
            CHCHR channel_ctrl;
        };

        //0: Highest, 7: Lowest
        typedef uint32_t Priority;
        static constexpr Priority HighestPriority = 0;
        static constexpr Priority LowestPriority  = 7;

        struct __no_align DMAControlRegister : public ComplexBitMap<uint32_t> {
            __io_port_inherit_complex_bit_map(DMAControlRegister);

            static constexpr auto OTCEnable      = Bit<uint32_t>(27);
            static constexpr auto OTCPriority    = BitRange<Priority>::from_to(24, 26);

            static constexpr auto PIOEnable      = Bit<uint32_t>(23);
            static constexpr auto PIOPriority    = BitRange<Priority>::from_to(20, 22);

            static constexpr auto SPUEnable      = Bit<uint32_t>(19);
            static constexpr auto SPUPriority    = BitRange<Priority>::from_to(16, 18);

            static constexpr auto CDROMEnable     = Bit<uint32_t>(15);
            static constexpr auto CDROMPriority   = BitRange<Priority>::from_to(12, 14);

            static constexpr auto GPUEnable       = Bit<uint32_t>(11);
            static constexpr auto GPUPriority     = BitRange<Priority>::from_to(8, 10);

            static constexpr auto MDECoutEnable   = Bit<uint32_t>(7);
            static constexpr auto MDECoutPriority = BitRange<Priority>::from_to(4, 6);

            static constexpr auto MDECinEnable    = Bit<uint32_t>(3);
            static constexpr auto MDECinPriority  = BitRange<Priority>::from_to(0, 2);
        };

        struct __no_align DMAInterruptRegister : public ComplexBitMap<uint32_t> {
            __io_port_inherit_complex_bit_map(DMAInterruptRegister);

            static constexpr auto MasterEnable     = Bit<uint32_t>(31);
            static constexpr auto Flags            = BitRange<uint32_t>::from_to(24, 30);
            static constexpr auto MasterEnableDPCR = Bit<uint32_t>(23);
            static constexpr auto EnableDPCR       = BitRange<uint32_t>::from_to(16, 22);
            static constexpr auto ForceIRQ         = Bit<uint32_t>(15);
        };

        __declare_io_port_global(Registers, MDECin,  0x1F801080);
        __declare_io_port_global(Registers, MDECout, 0x1F801090);
        __declare_io_port_global(Registers, GPU,     0x1F8010A0);
        __declare_io_port_global(Registers, CDROM,   0x1F8010B0);
        __declare_io_port_global(Registers, SPU,     0x1F8010C0);
        __declare_io_port_global(Registers, PIO,     0x1F8010D0);
        __declare_io_port_global(Registers, OTC,     0x1F8010E0);

        __declare_io_port_global(DMAControlRegister,   DPCR, 0x1F8010F0);
        __declare_io_port_global(DMAInterruptRegister, DICR, 0x1F8010F4);
    }
}

#endif //!__JABYENGINE_DMA_IO_HPP__