#ifndef __JABYENGINE_GPU_IO_HPP__
#define __JABYENGINE_GPU_IO_HPP__
#include "IOPort.hpp"

namespace GPU {
    namespace Port {
        enum struct SemiTransparency {
            B_Half_add_F_Half = 0,
            B_add_F           = 1,
            B_sub_F           = 2,
            B_add_F_Quarter   = 3,
        };

        enum struct TexturePageColor {
             _4bit = 0,
             _8bit = 1,
            _15bit = 2,
        };

        enum struct HorizontalResolution {
            _256 = 0,
            _320 = 1,
            _512 = 2,
            _640 = 3,
        };

        enum struct VerticalResolution {
            _240 = 0,
            _480 = 1
        };

        enum struct DMADirection {
            Off     = 0,
            Unknown = 1,
            CPU2GPU = 2,
            GPU2CPU = 3,
        };

        enum struct DisplayState {
            On  = 0,
            Off = 1
        };

        namespace Command {
            static constexpr uint32_t construct_cmd(uint8_t cmd, uint32_t value) {
                return ((cmd << 24) | value);
            }

            struct __no_align GP0 : public ComplexBitMap<uint32_t> {
                __io_port_inherit_complex_bit_map(GP0);
            };

            struct __no_align GP1 : public ComplexBitMap<uint32_t> {
                __io_port_inherit_complex_bit_map(GP1);

                static constexpr GP1 Reset() {
                    return {0};
                }

                static constexpr GP1 SetDisplayState(DisplayState state) {
                    return {construct_cmd(0x03, static_cast<uint32_t>(state))};
                }
            };
        }

        struct __no_align GPUStatusRegister : public ComplexBitMap<uint32_t> {
            static constexpr auto DrawingOddLinesInterlaced    = Bit<uint32_t>(31);
            static constexpr auto DMADirectionValue            = BitRange<DMADirection>::from_to(29, 30);
            static constexpr auto DMAReady                     = Bit<uint32_t>(28);
            static constexpr auto VRAMtoCPUtransferReay        = Bit<uint32_t>(27);
            static constexpr auto GP0ReadyForCMD               = Bit<uint32_t>(26);
            static constexpr auto FifoNotFull                  = Bit<uint32_t>(25); // Only for Fifo
            static constexpr auto InterruptRequest             = Bit<uint32_t>(24);
            static constexpr auto DisplayDisabled              = Bit<uint32_t>(23);
            static constexpr auto VerticalInterlaceOn          = Bit<uint32_t>(22);
            static constexpr auto DisplayAreaColorDepth24bit   = Bit<uint32_t>(21);
            static constexpr auto VideoModePal                 = Bit<uint32_t>(20);
            static constexpr auto VerticalResolutionValue      = BitRange<VerticalResolution>::from_to(19, 19);
            static constexpr auto HorizontalResolutionValue    = BitRange<HorizontalResolution>::from_to(17, 18);
            static constexpr auto HorizontalResolution368      = Bit<uint32_t>(16);
            static constexpr auto TexturesDisabled             = Bit<uint32_t>(15);
            static constexpr auto NotDrawingMaskedPixels       = Bit<uint32_t>(12);
            static constexpr auto MaskBitSetDuringDrawEnabled  = Bit<uint32_t>(11);
            static constexpr auto DrawingToDisplayAreadAllowed = Bit<uint32_t>(10);
            static constexpr auto DitherEnabled                = Bit<uint32_t>(9);
            static constexpr auto TexturePageColorValue        = BitRange<TexturePageColor>::from_to(7, 8);
            static constexpr auto SemiTransparencyValue        = BitRange<SemiTransparency>::from_to(5, 6);
            static constexpr auto TexturePageY                 = BitRange<uint32_t>::from_to(4, 4); // N*256
            static constexpr auto TexturePageX                 = BitRange<uint32_t>::from_to(0, 3); // N*64

            static constexpr auto VerticalResolution480 = Bit<uint32_t>(19);
            static constexpr auto TexturePageY256       = Bit<uint32_t>(4);
        };

        __declare_io_port_global(Command::GP0, GP0, 0x1F801810);
        __declare_io_port_global(Command::GP1, GP1, 0x1F801814);

        __declare_io_port_global_const(uint32_t,          GPUREAD, 0x1F801810);
        __declare_io_port_global_const(GPUStatusRegister, GPUSTAT, 0x1F801814);
    }
}

#endif //!__JABYENGINE_GPU_IO_HPP__