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Add new IOPort design

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jaby
2023-01-15 16:49:38 +01:00
parent 509c25dfec
commit 3da34d0686
15 changed files with 143 additions and 240 deletions
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44
include/PSX/System/IOPorts/dma_io.hpp
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@@ -4,34 +4,26 @@
namespace JabyEngine {
namespace DMA_IO {
struct __no_align MADR : public ComplexBitMap<uint32_t> {
__io_port_inherit_complex_bit_map(MADR);
struct MADR : public ComplexBitMap<uint32_t> {
static constexpr auto MemoryAdr = BitRange<uint32_t>::from_to(0, 23);
};
struct __no_align BCR : public ComplexBitMap<uint32_t> {
__io_port_inherit_complex_bit_map(BCR);
struct BCR : public ComplexBitMap<uint32_t> {
struct __no_align SyncMode0 {
static constexpr auto NumberOfWords = BitRange<uint16_t>::from_to(0, 15);
static constexpr auto CD_OneBlock = Bit<uint16_t>(16);
};
struct __no_align SyncMode1 : public ComplexBitMap<uint32_t> {
__io_port_inherit_complex_bit_map(SyncMode1);
struct SyncMode1 : public ComplexBitMap<uint32_t> {
static constexpr auto BlockSize = BitRange<uint32_t>::from_to(0, 15);
static constexpr auto BlockAmount = BitRange<uint32_t>::from_to(16, 31);
};
struct __no_align SyncMode2 {
struct SyncMode2 {
};
};
struct __no_align CHCHR : public ComplexBitMap<uint32_t> {
__io_port_inherit_complex_bit_map(CHCHR);
struct CHCHR : public ComplexBitMap<uint32_t> {
enum _SyncMode {
Sync0 = 0, //Start immediately,
Sync1 = 1, //Sync blocks to DMA requests
@@ -60,34 +52,34 @@ namespace JabyEngine {
static constexpr auto ToMainRAM = !FromMainRAM;
static constexpr CHCHR StartMDECin() {
return ComplexBitMap{0x01000201};
return CHCHR{0x01000201};
}
static constexpr CHCHR StartMDECout() {
return ComplexBitMap{0x01000200};
return CHCHR{0x01000200};
}
static constexpr CHCHR StartGPUReceive() {
return ComplexBitMap{0x01000201};
return CHCHR{0x01000201};
}
static constexpr CHCHR StartCDROM() {
return ComplexBitMap{0x11000000};
return CHCHR{0x11000000};
}
static constexpr CHCHR StartSPUReceive() {
return ComplexBitMap{0x01000201};
return CHCHR{0x01000201};
}
static constexpr CHCHR StartOTC() {
return ComplexBitMap{0x11000002};
return CHCHR{0x11000002};
}
};
struct __no_align Registers {
IOPort<MADR> adr;
IOPort<BCR> block_ctrl;
IOPort<CHCHR> channel_ctrl;
IOPort<MADR::UnderlyingType, MADR> adr;
IOPort<BCR::UnderlyingType, BCR> block_ctrl;
IOPort<CHCHR::UnderlyingType, CHCHR> channel_ctrl;
};
//0: Highest, 7: Lowest
@@ -95,9 +87,7 @@ namespace JabyEngine {
static constexpr Priority HighestPriority = 0;
static constexpr Priority LowestPriority = 7;
struct __no_align DMAControlRegister : public ComplexBitMap<uint32_t> {
__io_port_inherit_complex_bit_map(DMAControlRegister);
struct DMAControlRegister : public ComplexBitMap<uint32_t> {
static constexpr auto OTCEnable = Bit<uint32_t>(27);
static constexpr auto OTCPriority = BitRange<Priority>::from_to(24, 26);
@@ -120,9 +110,7 @@ namespace JabyEngine {
static constexpr auto MDECinPriority = BitRange<Priority>::from_to(0, 2);
};
struct __no_align DMAInterruptRegister : public ComplexBitMap<uint32_t> {
__io_port_inherit_complex_bit_map(DMAInterruptRegister);
struct DMAInterruptRegister : public ComplexBitMap<uint32_t> {
static constexpr auto MasterEnable = Bit<uint32_t>(31);
static constexpr auto Flags = BitRange<uint32_t>::from_to(24, 30);
static constexpr auto MasterEnableDPCR = Bit<uint32_t>(23);