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Add new IOPort design

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jaby
2023-01-15 16:49:38 +01:00
parent 509c25dfec
commit 3da34d0686
15 changed files with 143 additions and 240 deletions
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37
include/PSX/System/IOPorts/gpu_io.hpp
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@@ -48,15 +48,14 @@ namespace JabyEngine {
};
struct Command {
struct __no_align GP0 : public ComplexBitMap<uint32_t> {
__io_port_inherit_complex_bit_map(GP0);
struct GP0 : public ComplexBitMap<uint32_t> {
static constexpr GP0 QuickFill(GPU::Color24 color) {
return ComplexBitMap{(0x02 << 24) | color.raw()};
return {(0x02 << 24) | color.raw()};
}
static constexpr GP0 CPU2VRAM_Blitting() {
return ComplexBitMap{(0b101u << 29)};
return {(0b101u << 29)};
}
static constexpr GP0 DrawAreaTemplate(uint8_t code, uint16_t x, uint16_t y) {
@@ -64,7 +63,7 @@ namespace JabyEngine {
constexpr auto Y = BitRange<uint32_t>::from_to(10, 18);
constexpr auto X = BitRange<uint32_t>::from_to(0, 9);
return ComplexBitMap<uint32_t>::with(Command.with(code), Y.with(y), X.with(x));
return {GP0::with(Command.with(code), Y.with(y), X.with(x))};
}
static constexpr GP0 DrawAreaTopLeft(uint16_t x, uint16_t y) {
@@ -76,65 +75,63 @@ namespace JabyEngine {
}
static constexpr GP0 TopLeftPosition(uint16_t x, uint16_t y) {
return ComplexBitMap{static_cast<uint32_t>((y << 16u) | x)};
return {static_cast<uint32_t>((y << 16u) | x)};
}
static constexpr GP0 WidthHeight(uint16_t w, uint16_t h) {
return ComplexBitMap{static_cast<uint32_t>((h << 16u) | w)};
return {static_cast<uint32_t>((h << 16u) | w)};
}
};
struct __no_align GP1 : public ComplexBitMap<uint32_t> {
__io_port_inherit_complex_bit_map(GP1);
struct GP1 : public ComplexBitMap<uint32_t> {
static constexpr uint32_t construct_cmd(uint8_t cmd, uint32_t value) {
return ((cmd << 24) | value);
}
static constexpr GP1 Reset() {
return ComplexBitMap{0};
return {0};
}
static constexpr GP1 ResetCMDBufer() {
return ComplexBitMap{construct_cmd(0x01, 0)};
return {construct_cmd(0x01, 0)};
}
static constexpr GP1 SetDisplayState(DisplayState state) {
return ComplexBitMap{construct_cmd(0x03, static_cast<uint32_t>(state))};
return {construct_cmd(0x03, static_cast<uint32_t>(state))};
}
static constexpr GP1 DMADirection(DMADirection dir) {
return ComplexBitMap{construct_cmd(0x04, static_cast<uint32_t>(dir))};
return {construct_cmd(0x04, static_cast<uint32_t>(dir))};
}
static constexpr GP1 DisplayArea(uint16_t x, uint16_t y) {
constexpr auto X = BitRange<uint32_t>::from_to(0, 9);
constexpr auto Y = BitRange<uint32_t>::from_to(10, 18);
return ComplexBitMap{construct_cmd(0x05, ComplexBitMap<uint32_t>::with(X.with(x), Y.with(y)).raw)};
return {construct_cmd(0x05, ComplexBitMap<uint32_t>::with(X.with(x), Y.with(y)).raw)};
}
static constexpr GP1 HorizontalDisplayRange(uint32_t x1, uint32_t x2) {
constexpr auto X1 = BitRange<uint32_t>::from_to(0, 11);
constexpr auto X2 = BitRange<uint32_t>::from_to(12, 23);
return ComplexBitMap{construct_cmd(0x06, ComplexBitMap<uint32_t>::with(X1.with(x1), X2.with(x2)).raw)};
return {construct_cmd(0x06, ComplexBitMap<uint32_t>::with(X1.with(x1), X2.with(x2)).raw)};
}
static constexpr GP1 VerticalDisplayRange(uint32_t y1, uint32_t y2) {
constexpr auto Y1 = BitRange<uint32_t>::from_to(0, 9);
constexpr auto Y2 = BitRange<uint32_t>::from_to(10, 19);
return ComplexBitMap{construct_cmd(0x07, ComplexBitMap<uint32_t>::with(Y1.with(y1), Y2.with(y2)).raw)};
return {construct_cmd(0x07, ComplexBitMap<uint32_t>::with(Y1.with(y1), Y2.with(y2)).raw)};
}
static constexpr GP1 DisplayMode(uint32_t mode) {
return ComplexBitMap{construct_cmd(0x08, mode)};
return {construct_cmd(0x08, mode)};
}
};
};
struct __no_align GPUStatusRegister : public ComplexBitMap<uint32_t> {
struct GPUStatusRegister : public ComplexBitMap<uint32_t> {
static constexpr auto DrawingOddLinesInterlaced = Bit<uint32_t>(31);
static constexpr auto DMADirectionValue = BitRange<DMADirection>::from_to(29, 30);
static constexpr auto DMAReady = Bit<uint32_t>(28);
@@ -166,7 +163,7 @@ namespace JabyEngine {
__declare_io_port_global(Command::GP0, GP0, 0x1F801810);
__declare_io_port_global(Command::GP1, GP1, 0x1F801814);
__declare_io_port_global_const(uint32_t, GPUREAD, 0x1F801810);
__declare_io_port_global_const_simple(uint32_t, GPUREAD, 0x1F801810);
__declare_io_port_global_const(GPUStatusRegister, GPUSTAT, 0x1F801814);
}
}