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Update GPU IOs (What a pain)

This commit is contained in:
jaby 2024-09-28 17:49:04 +02:00
parent 54b12b13e9
commit 3fab693049
9 changed files with 319 additions and 239 deletions
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16
include/PSX/GPU/Primitives/primitive_gpu_commands.hpp
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@ -8,23 +8,23 @@ namespace JabyEngine {
struct TexPage : public internal::LinkedElementCreator<TexPage> { struct TexPage : public internal::LinkedElementCreator<TexPage> {
static constexpr bool is_render_primitive = true; static constexpr bool is_render_primitive = true;
struct GPU_IO::GP0 value; GPU_IO_Values::GP0 value;
static constexpr TexPage create(const PositionU16& tex_pos, TextureColorMode tex_color, SemiTransparency transparency = SemiTransparency::B_Half_add_F_Half, bool dither = false) { static constexpr TexPage create(const PositionU16& tex_pos, TextureColorMode tex_color, SemiTransparency transparency = SemiTransparency::B_Half_add_F_Half, bool dither = false) {
return TexPage{.value = GPU_IO::Command::TexPage(tex_pos, transparency, tex_color, dither, false)}; return TexPage{.value = GPU_IO_Values::GP0::TexPage(tex_pos, transparency, tex_color, dither, false)};
} }
}; };
struct CPU2VRAM { struct CPU2VRAM {
struct GPU_IO::GP0 cmd; GPU_IO_Values::GP0 cmd;
struct GPU_IO::GP0 pos; GPU_IO_Values::GP0 pos;
struct GPU_IO::GP0 size; GPU_IO_Values::GP0 size;
static constexpr CPU2VRAM create(const AreaU16& dst) { static constexpr CPU2VRAM create(const AreaU16& dst) {
return CPU2VRAM{ return CPU2VRAM{
.cmd = GPU_IO::Command::CPU2VRAM_Blitting(), .cmd = GPU_IO_Values::GP0::CPU2VRAMBlitting(),
.pos = GPU_IO::Command::TopLeftPosition(dst.position), .pos = GPU_IO_Values::GP0::PostionTopLeft(dst.position),
.size = GPU_IO::Command::WidthHeight(dst.size) .size = GPU_IO_Values::GP0::WidthHeight(dst.size)
}; };
} }
}; };

4
include/PSX/GPU/gpu.hpp
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@ -33,11 +33,11 @@ namespace JabyEngine {
} }
static void enable() { static void enable() {
GPU_IO::GP1.write(GPU_IO::Command::SetDisplayState(GPU_IO::DisplayState::On)); GPU_IO::GP1.set_display_state(GPU_IO::DisplayMode::State::On);
} }
static void disable() { static void disable() {
GPU_IO::GP1.write(GPU_IO::Command::SetDisplayState(GPU_IO::DisplayState::Off)); GPU_IO::GP1.set_display_state(GPU_IO::DisplayMode::State::Off);
} }
static void set_offset(int16_t x, int16_t y); static void set_offset(int16_t x, int16_t y);

220
include/PSX/System/IOPorts/IOValues/gpu_io_values.hpp Normal file
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@ -0,0 +1,220 @@
#pragma once
#include "../../../GPU/gpu_types.hpp"
#include "../ioport.hpp"
namespace JabyEngine {
namespace GPU_IO_Values {
namespace internal {
template<typename T>
static constexpr T construct_cmd(uint32_t cmd, uint32_t value) {
return T::from(T::ID.with(cmd), T::Value.with(value));
}
}
__declare_io_value(DisplayMode, uint32_t) {
enum AreaColorDepth {
$15bit = 0,
$24bit = 1,
};
enum State {
On = 0,
Off = 1
};
enum HorizontalResolution {
$256 = 0,
$320 = 1,
$512 = 2,
$640 = 3,
};
enum struct TVEncoding {
NTSC = 0,
PAL = 1,
};
enum VerticalResolution {
$240 = 0,
$480 = 1
};
static constexpr auto HorizontalResolution368 = Bit(6);
static constexpr auto VerticalInterlace = Bit(5);
static constexpr auto DisplayAreaColorDepth = BitRange::from_to(4, 4);
static constexpr auto VideoMode = BitRange::from_to(3, 3);
static constexpr auto VerticalResolution = BitRange::from_to(2, 2);
static constexpr auto HorizontalResolution = BitRange::from_to(0, 1);
static constexpr DisplayMode PAL() {
return DisplayMode::from(
HorizontalResolution.with(HorizontalResolution::$320),
VerticalResolution.with(VerticalResolution::$240),
VideoMode.with(TVEncoding::PAL),
DisplayAreaColorDepth.with(AreaColorDepth::$15bit)
);
}
static constexpr DisplayMode NTSC() {
return DisplayMode::from(
HorizontalResolution.with(HorizontalResolution::$320),
VerticalResolution.with(VerticalResolution::$240),
VideoMode.with(TVEncoding::NTSC),
DisplayAreaColorDepth.with(AreaColorDepth::$15bit)
);
}
};
__declare_io_value(GPUREAD, uint32_t) {
};
__declare_io_value(GPUSTAT, uint32_t) {
enum DMADirection {
Off = 0,
Fifo = 1,
CPU2GPU = 2,
GPU2CPU = 3,
};
static constexpr auto DrawingOddLinesInterlaced = Bit(31);
static constexpr auto DMADirectionValue = BitRange::from_to(29, 30);
static constexpr auto DMAReady = Bit(28);
static constexpr auto VRAMtoCPUtransferReay = Bit(27);
static constexpr auto GP0ReadyForCMD = Bit(26);
static constexpr auto FifoNotFull = Bit(25); // Only for Fifo
static constexpr auto InterruptRequest = Bit(24);
static constexpr auto DisplayDisabled = Bit(23);
static constexpr auto VerticalInterlaceOn = Bit(22);
static constexpr auto DisplayAreaColorDepth = BitRange::from_to(21, 21);
static constexpr auto VideoModePal = Bit(20);
static constexpr auto VerticalResolutionValue = BitRange::from_to(19, 19);
static constexpr auto HorizontalResolutionValue = BitRange::from_to(17, 18);
static constexpr auto HorizontalResolution368 = Bit(16);
static constexpr auto TexturesDisabled = Bit(15);
static constexpr auto NotDrawingMaskedPixels = Bit(12);
static constexpr auto MaskBitSetDuringDrawEnabled = Bit(11);
static constexpr auto DrawingToDisplayAreadAllowed = Bit(10);
static constexpr auto DitherEnabled = Bit(9);
static constexpr auto TexturePageColorValue = BitRange::from_to(7, 8);
static constexpr auto SemiTransparencyValue = BitRange::from_to(5, 6);
static constexpr auto TexturePageY = BitRange::from_to(4, 4); // N*256
static constexpr auto TexturePageX = BitRange::from_to(0, 3); // N*64
static constexpr auto VerticalResolution480 = Bit(19);
static constexpr auto TexturePageY256 = Bit(4);
};
__declare_io_value(GP0, uint32_t) {
static constexpr auto ID = BitRange::from_to(24, 31);
static constexpr auto Value = BitRange::from_to(0, 23);
static constexpr GP0 DrawAreaTemplate(uint8_t code, uint16_t x, uint16_t y) {
constexpr auto Command = BitRange::from_to(24, 31);
constexpr auto Y = BitRange::from_to(10, 18);
constexpr auto X = BitRange::from_to(0, 9);
return internal::construct_cmd<GP0>(code, Y.as_value(static_cast<uint32_t>(y)) | X.as_value(static_cast<uint32_t>(x)));
}
static constexpr GP0 ClearCache() {
return internal::construct_cmd<GP0>(0x01, 0x0);
}
static constexpr GP0 QuickFill(GPU::Color24 color) {
return internal::construct_cmd<GP0>(0x02, color.raw());
}
static constexpr GP0 VRAM2VRAMBlitting() {
return internal::construct_cmd<GP0>(0x80, 0);
}
static constexpr GP0 CPU2VRAMBlitting() {
return internal::construct_cmd<GP0>(0xA0, 0);
}
static constexpr GP0 TexPage(const GPU::PositionU16& page_pos, GPU::SemiTransparency transparency, GPU::TextureColorMode tex_color, bool dither, bool draw_on_display_area) {
constexpr auto TexXRange = BitRange::from_to(0, 3);
constexpr auto TexYRange = BitRange::from_to(4, 4);
constexpr auto TransparencyRange = BitRange::from_to(5, 6);
constexpr auto TextureColorRange = BitRange::from_to(7, 8);
constexpr auto DitherBit = BitRange::from_to(9, 9);
constexpr auto DrawOnDisplayAreaBit = BitRange::from_to(10, 10);
return internal::construct_cmd<GP0>(0xE1,
TexXRange.as_value(page_pos.x >> 6) | TexYRange.as_value(page_pos.y >> 8) |
TransparencyRange.as_value(static_cast<uint32_t>(transparency)) | TextureColorRange.as_value(static_cast<uint32_t>(tex_color)) |
DitherBit.as_value(static_cast<uint32_t>(dither)) | DrawOnDisplayAreaBit.as_value(static_cast<uint32_t>(draw_on_display_area))
);
}
static constexpr GP0 DrawAreaTopLeft(const GPU::PositionU16& position) {
return GP0::DrawAreaTemplate(0xE3, position.x, position.y);
}
static constexpr GP0 DrawAreaBottomRight(const GPU::PositionU16& position) {
return GP0::DrawAreaTemplate(0xE4, position.x, position.y);
}
static constexpr GP0 DrawOffset(const GPU::PositionI16& offset) {
constexpr auto X = BitRange::from_to(0, 10);
constexpr auto Y = BitRange::from_to(11, 21);
return internal::construct_cmd<GPU_IO_Values::GP0>(0xE5, X.as_value(static_cast<int32_t>(offset.x)) | Y.as_value(static_cast<int32_t>(offset.y)));
}
static constexpr GP0 PostionTopLeft(const GPU::PositionU16& position) {
return GP0{(static_cast<uint32_t>(position.y) << 16u) | position.x};
}
static constexpr GP0 WidthHeight(const GPU::SizeU16& size) {
return GP0{(static_cast<uint32_t>(size.height) << 16u) | size.width};
}
};
__declare_io_value(GP1, uint32_t) {
static constexpr auto ID = BitRange::from_to(24, 31);
static constexpr auto Value = BitRange::from_to(0, 23);
static constexpr GP1 Reset() {
return GP1{0};
}
static constexpr GP1 ResetCMDBuffer() {
return internal::construct_cmd<GP1>(0x01, 0);
}
static constexpr GP1 DisplayState(DisplayMode::State state) {
return internal::construct_cmd<GP1>(0x03, static_cast<uint32_t>(state));
}
static constexpr GP1 DMADirection(GPUSTAT::DMADirection dir) {
return internal::construct_cmd<GP1>(0x04, dir);
}
static constexpr GP1 DisplayArea(const GPU::PositionU16& position) {
constexpr auto X = BitRange::from_to(0, 9);
constexpr auto Y = BitRange::from_to(10, 18);
return internal::construct_cmd<GP1>(0x05, X.as_value(static_cast<uint32_t>(position.x)) | Y.as_value(static_cast<uint32_t>(position.y)));
}
static constexpr GP1 HorizontalDisplayRange(uint16_t x1, uint16_t x2) {
constexpr auto X1 = BitRange::from_to(0, 11);
constexpr auto X2 = BitRange::from_to(12, 23);
return internal::construct_cmd<GP1>(0x06, X1.as_value(static_cast<uint32_t>(x1)) | X2.as_value(static_cast<uint32_t>(x2)));
}
static constexpr GP1 VerticalDisplayRange(uint16_t y1, uint16_t y2) {
constexpr auto Y1 = BitRange::from_to(0, 9);
constexpr auto Y2 = BitRange::from_to(10, 19);
return internal::construct_cmd<GP1>(0x07, Y1.as_value(static_cast<uint32_t>(y1)) | Y2.as_value(static_cast<uint32_t>(y2)));
}
static constexpr GP1 DisplayMode(GPU_IO_Values::DisplayMode mode) {
return internal::construct_cmd<GP1>(0x08, mode.raw);
}
};
}
}

2
include/PSX/System/IOPorts/IOValues/spu_io_values.hpp
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@ -200,7 +200,7 @@ namespace JabyEngine {
static constexpr auto Direction = Bit(13); static constexpr auto Direction = Bit(13);
static constexpr auto Phase = Bit(12); static constexpr auto Phase = Bit(12);
static constexpr auto Shift = BitRange::from_to(2, 6); static constexpr auto Shift = BitRange::from_to(2, 6);
static constexpr auto Step = BitRange::from_to(0, 1); static constexpr auto Step = BitRange::from_to(0, 1);
}; };
static constexpr SweepVolume create(SimpleVolume volume) { static constexpr SweepVolume create(SimpleVolume volume) {

263
include/PSX/System/IOPorts/gpu_io.hpp
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@ -1,230 +1,93 @@
#pragma once #pragma once
#include "ioport.hpp" #include "IOValues/gpu_io_values.hpp"
#include "../../GPU/gpu_types.hpp"
namespace JabyEngine { namespace JabyEngine {
namespace GPU_IO { namespace GPU_IO {
enum struct DisplayAreaColorDepth { using namespace GPU_IO_Values;
$15bit = 0,
$24bit = 1,
};
enum struct HorizontalResolution { struct GP0IO : public IOPort<GPU_IO_Values::GP0> {
$256 = 0, void clear_cache() {
$320 = 1, this->write(GPU_IO_Values::GP0::ClearCache());
$512 = 2,
$640 = 3,
};
enum struct VerticalResolution {
$240 = 0,
$480 = 1
};
enum struct DMADirection {
Off = 0,
Fifo = 1,
CPU2GPU = 2,
GPU2CPU = 3,
};
enum struct DisplayState {
On = 0,
Off = 1
};
__declare_io_value(DisplayMode, uint32_t) {
enum struct TVEncoding {
NTSC = 0,
PAL = 1,
};
static constexpr auto HorizontalResolution368 = Bit(6);
static constexpr auto VerticalInterlace = Bit(5);
static constexpr auto DisplayAreaColorDepth = BitRange::from_to(4, 4);
static constexpr auto VideoMode = BitRange::from_to(3, 3);
static constexpr auto VerticalResolution = BitRange::from_to(2, 2);
static constexpr auto HorizontalResolution = BitRange::from_to(0, 1);
static constexpr DisplayMode PAL() {
return DisplayMode::from(
HorizontalResolution.with(GPU_IO::HorizontalResolution::$320),
VerticalResolution.with(GPU_IO::VerticalResolution::$240),
VideoMode.with(TVEncoding::PAL),
DisplayAreaColorDepth.with(GPU_IO::DisplayAreaColorDepth::$15bit)
);
} }
static constexpr DisplayMode NTSC() { void quick_fill(GPU::Color24 color) {
return DisplayMode::from( this->write(GPU_IO_Values::GP0::QuickFill(color));
HorizontalResolution.with(GPU_IO::HorizontalResolution::$320), }
VerticalResolution.with(GPU_IO::VerticalResolution::$240),
VideoMode.with(TVEncoding::NTSC), void set_vram2vram_blitting() {
DisplayAreaColorDepth.with(GPU_IO::DisplayAreaColorDepth::$15bit) this->write(GPU_IO_Values::GP0::VRAM2VRAMBlitting());
); }
void set_cpu2vram_blitting() {
this->write(GPU_IO_Values::GP0::CPU2VRAMBlitting());
}
void set_tex_page(const GPU::PositionU16& page_pos, GPU::SemiTransparency transparency, GPU::TextureColorMode tex_color, bool dither, bool draw_on_display_area) {
this->write(GPU_IO_Values::GP0::TexPage(page_pos, transparency, tex_color, dither, draw_on_display_area));
}
void set_draw_area_top_left(const GPU::PositionU16& position) {
this->write(GPU_IO_Values::GP0::DrawAreaTopLeft(position));
}
void set_draw_area_bottom_right(const GPU::PositionU16& position) {
this->write(GPU_IO_Values::GP0::DrawAreaBottomRight(position));
}
void set_draw_offset(const GPU::PositionI16& offset) {
this->write(GPU_IO_Values::GP0::DrawOffset(offset));
}
void pass_top_left_position(const GPU::PositionU16& position) {
this->write(GPU_IO_Values::GP0::PostionTopLeft(position));
}
void pass_width_height(const GPU::SizeU16& size) {
this->write(GPU_IO_Values::GP0::WidthHeight(size));
} }
}; };
__declare_io_value(GP0, uint32_t) { struct GP1IO : public IOPort<GPU_IO_Values::GP1> {
static constexpr auto ID = BitRange::from_to(24, 31); void reset() {
static constexpr auto Value = BitRange::from_to(0, 23); this->write(GPU_IO_Values::GP1::Reset());
};
__declare_io_value(GP1, uint32_t) {
static constexpr auto ID = BitRange::from_to(24, 31);
static constexpr auto Value = BitRange::from_to(0, 23);
};
struct Command {
struct Helper {
template<typename T>
static constexpr T construct_cmd(uint32_t cmd, uint32_t value) {
return T::from(T::ID.with(cmd), T::Value.with(value));
}
static constexpr struct GP0 DrawAreaTemplate(uint8_t code, uint16_t x, uint16_t y) {
constexpr auto Command = BitRange::from_to(24, 31);
constexpr auto Y = BitRange::from_to(10, 18);
constexpr auto X = BitRange::from_to(0, 9);
return construct_cmd<struct GP0>(code, Y.as_value(static_cast<uint32_t>(y)) | X.as_value(static_cast<uint32_t>(x)));
}
};
static constexpr struct GP0 ClearCache() {
return Helper::construct_cmd<struct GP0>(0x01, 0x0);
} }
static constexpr struct GP0 QuickFill(GPU::Color24 color) { void reset_cmd_buffer() {
return Helper::construct_cmd<struct GP0>(0x02, color.raw()); this->write(GPU_IO_Values::GP1::ResetCMDBuffer());
} }
static constexpr struct GP0 VRAM2VRAM_Blitting() { void set_display_state(GPU_IO_Values::DisplayMode::State state) {
return Helper::construct_cmd<struct GP0>(0x80, 0); this->write(GPU_IO_Values::GP1::DisplayState(state));
} }
static constexpr struct GP0 CPU2VRAM_Blitting() { void set_dma_direction(GPU_IO_Values::GPUSTAT::DMADirection dir) {
return Helper::construct_cmd<struct GP0>(0xA0, 0); this->write(GPU_IO_Values::GP1::DMADirection(dir));
} }
static constexpr struct GP0 TexPage(const GPU::PositionU16& page_pos, GPU::SemiTransparency transparency, GPU::TextureColorMode tex_color, bool dither, bool draw_on_display_area) { void set_display_area(const GPU::PositionU16& position) {
constexpr auto TexXRange = BitRange::from_to(0, 3); this->write(GPU_IO_Values::GP1::DisplayArea(position));
constexpr auto TexYRange = BitRange::from_to(4, 4);
constexpr auto TransparencyRange = BitRange::from_to(5, 6);
constexpr auto TextureColorRange = BitRange::from_to(7, 8);
constexpr auto DitherBit = BitRange::from_to(9, 9);
constexpr auto DrawOnDisplayAreaBit = BitRange::from_to(10, 10);
return Helper::construct_cmd<struct GP0>(0xE1,
TexXRange.as_value(page_pos.x >> 6) | TexYRange.as_value(page_pos.y >> 8) |
TransparencyRange.as_value(static_cast<uint32_t>(transparency)) | TextureColorRange.as_value(static_cast<uint32_t>(tex_color)) |
DitherBit.as_value(static_cast<uint32_t>(dither)) | DrawOnDisplayAreaBit.as_value(static_cast<uint32_t>(draw_on_display_area))
);
} }
static constexpr struct GP0 DrawAreaTopLeft(const GPU::PositionU16& position) { void set_horizontal_display_range(uint16_t x1, uint16_t x2) {
return Helper::DrawAreaTemplate(0xE3, position.x, position.y); this->write(GPU_IO_Values::GP1::HorizontalDisplayRange(x1, x2));
} }
static constexpr struct GP0 DrawAreaBottomRight(const GPU::PositionU16& position) { void set_vertical_display_range(uint16_t y1, uint16_t y2) {
return Helper::DrawAreaTemplate(0xE4, position.x, position.y); this->write(GPU_IO_Values::GP1::VerticalDisplayRange(y1, y2));
} }
static constexpr struct GP0 SetDrawOffset(const GPU::PositionI16& offset) { void set_display_mode(GPU_IO_Values::DisplayMode mode) {
constexpr auto X = BitRange::from_to(0, 10); this->write(GPU_IO_Values::GP1::DisplayMode(mode));
constexpr auto Y = BitRange::from_to(11, 21);
return Helper::construct_cmd<struct GP0>(0xE5, X.as_value(static_cast<int32_t>(offset.x)) | Y.as_value(static_cast<int32_t>(offset.y)));
}
static constexpr struct GP0 TopLeftPosition(const GPU::PositionU16& position) {
return {(static_cast<uint32_t>(position.y) << 16u) | position.x};
}
static constexpr struct GP0 WidthHeight(const GPU::SizeU16& size) {
return {(static_cast<uint32_t>(size.height) << 16u) | size.width};
}
static constexpr struct GP1 Reset() {
return {0};
}
static constexpr struct GP1 ResetCMDBufer() {
return Helper::construct_cmd<struct GP1>(0x01, 0);
}
static constexpr struct GP1 SetDisplayState(DisplayState state) {
return Helper::construct_cmd<struct GP1>(0x03, static_cast<uint32_t>(state));
}
static constexpr struct GP1 DMADirection(DMADirection dir) {
return Helper::construct_cmd<struct GP1>(0x04, static_cast<uint32_t>(dir));
}
static constexpr struct GP1 DisplayArea(const GPU::PositionU16& position) {
constexpr auto X = BitRange::from_to(0, 9);
constexpr auto Y = BitRange::from_to(10, 18);
return Helper::construct_cmd<struct GP1>(0x05, X.as_value(static_cast<uint32_t>(position.x)) | Y.as_value(static_cast<uint32_t>(position.y)));
}
static constexpr struct GP1 HorizontalDisplayRange(uint16_t x1, uint16_t x2) {
constexpr auto X1 = BitRange::from_to(0, 11);
constexpr auto X2 = BitRange::from_to(12, 23);
return Helper::construct_cmd<struct GP1>(0x06, X1.as_value(static_cast<uint32_t>(x1)) | X2.as_value(static_cast<uint32_t>(x2)));
}
static constexpr struct GP1 VerticalDisplayRange(uint16_t y1, uint16_t y2) {
constexpr auto Y1 = BitRange::from_to(0, 9);
constexpr auto Y2 = BitRange::from_to(10, 19);
return Helper::construct_cmd<struct GP1>(0x07, Y1.as_value(static_cast<uint32_t>(y1)) | Y2.as_value(static_cast<uint32_t>(y2)));
}
static constexpr struct GP1 DisplayMode(DisplayMode mode) {
return Helper::construct_cmd<struct GP1>(0x08, mode.raw);
} }
}; };
using GPUREAD_IO = IOPort<GPU_IO_Values::GPUREAD>;
__declare_io_value(GPUREAD, uint32_t) { using GPUSTAT_IO = IOPort<GPU_IO_Values::GPUSTAT>;
};
__declare_io_value(GPUSTAT, uint32_t) {
static constexpr auto DrawingOddLinesInterlaced = Bit(31);
static constexpr auto DMADirectionValue = BitRange::from_to(29, 30);
static constexpr auto DMAReady = Bit(28);
static constexpr auto VRAMtoCPUtransferReay = Bit(27);
static constexpr auto GP0ReadyForCMD = Bit(26);
static constexpr auto FifoNotFull = Bit(25); // Only for Fifo
static constexpr auto InterruptRequest = Bit(24);
static constexpr auto DisplayDisabled = Bit(23);
static constexpr auto VerticalInterlaceOn = Bit(22);
static constexpr auto DisplayAreaColorDepth = BitRange::from_to(21, 21);
static constexpr auto VideoModePal = Bit(20);
static constexpr auto VerticalResolutionValue = BitRange::from_to(19, 19);
static constexpr auto HorizontalResolutionValue = BitRange::from_to(17, 18);
static constexpr auto HorizontalResolution368 = Bit(16);
static constexpr auto TexturesDisabled = Bit(15);
static constexpr auto NotDrawingMaskedPixels = Bit(12);
static constexpr auto MaskBitSetDuringDrawEnabled = Bit(11);
static constexpr auto DrawingToDisplayAreadAllowed = Bit(10);
static constexpr auto DitherEnabled = Bit(9);
static constexpr auto TexturePageColorValue = BitRange::from_to(7, 8);
static constexpr auto SemiTransparencyValue = BitRange::from_to(5, 6);
static constexpr auto TexturePageY = BitRange::from_to(4, 4); // N*256
static constexpr auto TexturePageX = BitRange::from_to(0, 3); // N*64
static constexpr auto VerticalResolution480 = Bit(19);
static constexpr auto TexturePageY256 = Bit(4);
};
static constexpr size_t FIFOWordSize = 16; static constexpr size_t FIFOWordSize = 16;
__declare_io_port(, GP0, 0x1F801810); static auto& GP0 = __new_declare_io_port(GP0IO, 0x1F801810);
__declare_io_port(, GP1, 0x1F801814); static const auto& GPUREAD = __new_declare_io_port(GPUREAD_IO, 0x1F801810);
static auto& GP1 = __new_declare_io_port(GP1IO, 0x1F801814);
__declare_io_port(const, GPUREAD, 0x1F801810); static const auto& GPUSTAT = __new_declare_io_port(GPUSTAT_IO, 0x1F801814);
__declare_io_port(const, GPUSTAT, 0x1F801814);
} }
} }

2
mkfile/Makefile
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@ -47,7 +47,7 @@ ARCHFLAGS += -fno-stack-protector -nostdlib -ffreestanding
CCFLAGS_release += -O3 CCFLAGS_release += -O3
CCFLAGS_debug += -O0 CCFLAGS_debug += -O0
CXXFLAGS += -fno-exceptions -fno-rtti CXXFLAGS += -fno-exceptions -fno-rtti -fno-threadsafe-statics
CCFLAGS += -mno-gpopt -fomit-frame-pointer -ffunction-sections -fdata-sections CCFLAGS += -mno-gpopt -fomit-frame-pointer -ffunction-sections -fdata-sections
CCFLAGS += -fno-builtin -fno-strict-aliasing -Wno-attributes CCFLAGS += -fno-builtin -fno-strict-aliasing -Wno-attributes

33
src/Library/internal-include/GPU/gpu_internal.hpp
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@ -32,37 +32,34 @@ namespace JabyEngine {
} }
static void set_draw_area(const PositionU16& pos) { static void set_draw_area(const PositionU16& pos) {
const auto top_left = GPU_IO::Command::DrawAreaTopLeft(pos);
const auto bottom_right = GPU_IO::Command::DrawAreaBottomRight(pos.move((Display::Width - 1), (Display::Height - 1)));
wait_ready_for_CMD(); wait_ready_for_CMD();
GPU_IO::GP0.write(top_left); GPU_IO::GP0.set_draw_area_top_left(pos);
wait_ready_for_CMD(); wait_ready_for_CMD();
GPU_IO::GP0.write(bottom_right); GPU_IO::GP0.set_draw_area_bottom_right(pos.move((Display::Width - 1), (Display::Height - 1)));
} }
static void copy_vram_to_vram(const AreaU16& dst, const PositionU16& src) { static void copy_vram_to_vram(const AreaU16& dst, const PositionU16& src) {
wait_ready_for_CMD(); wait_ready_for_CMD();
GPU_IO::GP0.write(GPU_IO::Command::VRAM2VRAM_Blitting()); GPU_IO::GP0.set_vram2vram_blitting();
GPU_IO::GP0.write(GPU_IO::Command::TopLeftPosition(src)); GPU_IO::GP0.pass_top_left_position(src);
GPU_IO::GP0.write(GPU_IO::Command::TopLeftPosition(dst.position)); GPU_IO::GP0.pass_top_left_position(dst.position);
GPU_IO::GP0.write(GPU_IO::Command::WidthHeight(dst.size)); GPU_IO::GP0.pass_width_height(dst.size);
} }
static void quick_fill_fast(const Color24& color, const AreaU16& area) { static void quick_fill_fast(const Color24& color, const AreaU16& area) {
wait_ready_for_CMD(); wait_ready_for_CMD();
GPU_IO::GP0.write(GPU_IO::Command::QuickFill(color)); GPU_IO::GP0.quick_fill(color);
GPU_IO::GP0.write(GPU_IO::Command::TopLeftPosition(area.position)); GPU_IO::GP0.pass_top_left_position(area.position);
GPU_IO::GP0.write(GPU_IO::Command::WidthHeight(area.size)); GPU_IO::GP0.pass_width_height(area.size);
} }
static void set_draw_offset(const PositionI16& offset) { static void set_draw_offset(const PositionI16& offset) {
wait_ready_for_CMD(); wait_ready_for_CMD();
GPU_IO::GP0.write(GPU_IO::Command::SetDrawOffset(offset)); GPU_IO::GP0.set_draw_offset(offset);
} }
static void reset_cmd_buffer() { static void reset_cmd_buffer() {
GPU_IO::GP1.write(GPU_IO::Command::ResetCMDBufer()); GPU_IO::GP1.reset_cmd_buffer();
} }
struct DMA { struct DMA {
@ -81,7 +78,7 @@ namespace JabyEngine {
struct Receive { struct Receive {
static void prepare() { static void prepare() {
GPU_IO::GP1.write(GPU_IO::Command::DMADirection(GPU_IO::DMADirection::CPU2GPU)); GPU_IO::GP1.set_dma_direction(GPU_IO::GPUSTAT::DMADirection::CPU2GPU);
reset_cmd_buffer(); reset_cmd_buffer();
} }
@ -95,9 +92,9 @@ namespace JabyEngine {
static void set_dst(const PositionU16& position, const SizeU16& size) { static void set_dst(const PositionU16& position, const SizeU16& size) {
wait_ready_for_CMD(); wait_ready_for_CMD();
GPU_IO::GP0.write(GPU_IO::Command::CPU2VRAM_Blitting()); GPU_IO::GP0.set_cpu2vram_blitting();
GPU_IO::GP0.write(GPU_IO::Command::TopLeftPosition(position)); GPU_IO::GP0.pass_top_left_position(position);
GPU_IO::GP0.write(GPU_IO::Command::WidthHeight(size)); GPU_IO::GP0.pass_width_height(size);
} }
static void start(uint16_t blockCount, uint16_t wordsPerBlock = 0x10) { static void start(uint16_t blockCount, uint16_t wordsPerBlock = 0x10) {

8
src/Library/src/BootLoader/gpu_boot.cpp
View File

@ -47,8 +47,8 @@ namespace JabyEngine {
namespace GPU { namespace GPU {
using namespace JabyEngine::GPU; using namespace JabyEngine::GPU;
static void configurate_display() { static void configure_display() {
GPU_IO::GP1.write(GPU_IO::Command::DisplayMode(::JabyEngine::GPU::internal::Display::DisplayMode)); GPU_IO::GP1.set_display_mode(::JabyEngine::GPU::internal::Display::DisplayMode);
GPU::Display::set_offset(0, 0); GPU::Display::set_offset(0, 0);
} }
@ -92,8 +92,8 @@ namespace JabyEngine {
} }
void setup() { void setup() {
GPU_IO::GP1.write(GPU_IO::Command::Reset()); GPU_IO::GP1.reset();
configurate_display(); configure_display();
::JabyEngine::GPU::internal::Display::exchange_buffer_and_display(); ::JabyEngine::GPU::internal::Display::exchange_buffer_and_display();
GPU::internal::wait_ready_for_CMD(); GPU::internal::wait_ready_for_CMD();

10
src/Library/src/GPU/gpu.cpp
View File

@ -44,7 +44,7 @@ namespace JabyEngine {
GPU::internal::set_draw_area(GPU::PositionU16::create(0, draw_area_y)); GPU::internal::set_draw_area(GPU::PositionU16::create(0, draw_area_y));
PublicDisplay::current_id ^= 1; PublicDisplay::current_id ^= 1;
GPU_IO::GP1.write(GPU_IO::Command::DisplayArea(GPU::PositionU16::create(0, static_cast<uint16_t>((TexturePageHeight*PublicDisplay::current_id))))); GPU_IO::GP1.set_display_area(GPU::PositionU16::create(0, static_cast<uint16_t>((TexturePageHeight*PublicDisplay::current_id))));
return draw_area_y; return draw_area_y;
} }
@ -61,7 +61,7 @@ namespace JabyEngine {
wait_ready_for_CMD(); wait_ready_for_CMD();
#ifdef __SUPPORT_PS3__ #ifdef __SUPPORT_PS3__
// The PS3 needs explict change to FiFo // The PS3 needs explict change to FiFo
GPU_IO::GP1.write(GPU_IO::Command::DMADirection(GPU_IO::DMADirection::Fifo)); GPU_IO::GP1.set_dma_direction(GPU_IO::GPUSTAT::DMADirection::Fifo);
#endif // __SUPPORT_PS3__ #endif // __SUPPORT_PS3__
for(size_t n = 0; n < words; n++) { for(size_t n = 0; n < words; n++) {
@ -72,7 +72,7 @@ namespace JabyEngine {
void render_dma(const uint32_t* data) { void render_dma(const uint32_t* data) {
// DPCR already enabled // DPCR already enabled
DMA_IO::GPU.wait(); DMA_IO::GPU.wait();
GPU_IO::GP1.write(GPU_IO::Command::DMADirection(GPU_IO::DMADirection::CPU2GPU)); GPU_IO::GP1.set_dma_direction(GPU_IO::GPUSTAT::DMADirection::CPU2GPU);
DMA_IO::GPU.set_adr(reinterpret_cast<uintptr_t>(data)); DMA_IO::GPU.set_adr(reinterpret_cast<uintptr_t>(data));
DMA_IO::GPU.block_ctrl.write(DMA_IO::BCR::SyncMode2::for_gpu_cmd()); DMA_IO::GPU.block_ctrl.write(DMA_IO::BCR::SyncMode2::for_gpu_cmd());
@ -94,8 +94,8 @@ namespace JabyEngine {
x += (internal::Display::DisplayRange.x + Configuration::DisplayDefaultOffset.x); x += (internal::Display::DisplayRange.x + Configuration::DisplayDefaultOffset.x);
y += (internal::Display::DisplayRange.y + Configuration::DisplayDefaultOffset.y); y += (internal::Display::DisplayRange.y + Configuration::DisplayDefaultOffset.y);
GPU_IO::GP1.write(GPU_IO::Command::HorizontalDisplayRange((x << 3), (x + Display::Width + PS3_CorrectionX) << 3)); GPU_IO::GP1.set_horizontal_display_range((x << 3), (x + Display::Width + PS3_CorrectionX) << 3);
GPU_IO::GP1.write(GPU_IO::Command::VerticalDisplayRange(y, y + Display::Height + PS3_CorrectionY)); GPU_IO::GP1.set_vertical_display_range( y, y + Display::Height + PS3_CorrectionY);
} }
uint8_t swap_buffers_vsync(uint8_t syncs, bool clear_screen) { uint8_t swap_buffers_vsync(uint8_t syncs, bool clear_screen) {