Port DMA code
This commit is contained in:
@@ -4,130 +4,147 @@
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namespace JabyEngine {
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namespace DMA_IO {
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struct MADR : public ComplexBitMap<uint32_t> {
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static constexpr auto MemoryAdr = BitRange<uint32_t>::from_to(0, 23);
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};
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__declare_io_type(MADR, uint32_t,
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static constexpr auto MemoryAdr = IOValueSet::from_to(0, 23);
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);
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struct BCR : public ComplexBitMap<uint32_t> {
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__declare_io_type(BCR, uint32_t,
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struct __no_align SyncMode0 {
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static constexpr auto NumberOfWords = BitRange<uint16_t>::from_to(0, 15);
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static constexpr auto CD_OneBlock = Bit<uint16_t>(16);
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static constexpr auto NumberOfWords = IOValueSet::from_to(0, 15);
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static constexpr auto CD_OneBlock = IOBitSet(16);
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};
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struct SyncMode1 : public ComplexBitMap<uint32_t> {
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static constexpr auto BlockSize = BitRange<uint32_t>::from_to(0, 15);
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static constexpr auto BlockAmount = BitRange<uint32_t>::from_to(16, 31);
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static constexpr auto BlockSize = IOValueSet::from_to(0, 15);
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static constexpr auto BlockAmount = IOValueSet::from_to(16, 31);
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};
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struct SyncMode2 {
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};
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};
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);
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struct CHCHR : public ComplexBitMap<uint32_t> {
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enum _SyncMode {
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__declare_io_type(CHCHR, uint32_t,
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enum SyncMode_t {
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Sync0 = 0, //Start immediately,
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Sync1 = 1, //Sync blocks to DMA requests
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Sync2 = 2, //Linked List
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};
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static constexpr auto ManualStart = Bit<uint32_t>(28);
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static constexpr auto ManualStart = IOBitSet(28);
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static constexpr auto Start = Bit<uint32_t>(24);
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static constexpr auto Start = IOBitSet(24);
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static constexpr auto Busy = Start;
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static constexpr auto ChoppingCPUWindowSize = BitRange<uint32_t>::from_to(20, 22);
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static constexpr auto ChoppingDMAWindowSize = BitRange<uint32_t>::from_to(16, 18);
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static constexpr auto ChoppingCPUWindowSize = IOValueSet::from_to(20, 22);
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static constexpr auto ChoppingDMAWindowSize = IOValueSet::from_to(16, 18);
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static constexpr auto SyncMode = BitRange<_SyncMode>::from_to(9, 10);
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static constexpr auto SyncMode = IOValueSet::from_to(9, 10);
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static constexpr auto UseSyncMode0 = SyncMode.with(Sync0);
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static constexpr auto UseSyncMode1 = SyncMode.with(Sync1);
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static constexpr auto UseSyncMode2 = SyncMode.with(Sync2);
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static constexpr auto UseChopping = Bit<uint32_t>(8);
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static constexpr auto UseChopping = IOBitSet(8);
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static constexpr auto MemoryAdrDecreaseBy4 = Bit<uint32_t>(1);
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static constexpr auto MemoryAdrDecreaseBy4 = IOBitSet(1);
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static constexpr auto MemoryAdrIncreaseBy4 = !MemoryAdrDecreaseBy4;
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static constexpr auto FromMainRAM = Bit<uint32_t>(0);
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static constexpr auto FromMainRAM = IOBitSet(0);
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static constexpr auto ToMainRAM = !FromMainRAM;
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static constexpr CHCHR StartMDECin() {
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return CHCHR{0x01000201};
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static constexpr Self StartMDECin() {
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return Self{0x01000201};
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}
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static constexpr CHCHR StartMDECout() {
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return CHCHR{0x01000200};
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static constexpr Self StartMDECout() {
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return Self{0x01000200};
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}
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static constexpr CHCHR StartGPUReceive() {
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return CHCHR{0x01000201};
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static constexpr Self StartGPUReceive() {
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return Self{0x01000201};
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}
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static constexpr CHCHR StartCDROM() {
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return CHCHR{0x11000000};
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static constexpr Self StartCDROM() {
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return Self{0x11000000};
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}
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static constexpr CHCHR StartSPUReceive() {
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return CHCHR{0x01000201};
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static constexpr Self StartSPUReceive() {
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return Self{0x01000201};
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}
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static constexpr CHCHR StartOTC() {
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return CHCHR{0x11000002};
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static constexpr Self StartOTC() {
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return Self{0x11000002};
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}
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};
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);
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struct __no_align Registers {
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VolatileBitMapPOD<MADR> adr;
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VolatileBitMapPOD<BCR> block_ctrl;
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VolatileBitMapPOD<CHCHR> channel_ctrl;
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MADR_v adr;
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BCR_v block_ctrl;
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CHCHR_v channel_ctrl;
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void set_adr(uintptr_t adr) {
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this->adr.set(MADR_t::MemoryAdr.with(adr));
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}
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void wait() {
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while(this->channel_ctrl.is_set(CHCHR_t::Busy));
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}
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};
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// Those types do not need to be volatile because there members are
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typedef Registers MDECin_v;
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typedef Registers MDECout_v;
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typedef Registers GPU_v;
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typedef Registers CDROM_v;
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typedef Registers SPU_v;
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typedef Registers PIO_v;
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typedef Registers OTC_v;
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//0: Highest, 7: Lowest
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typedef uint32_t Priority;
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static constexpr Priority HighestPriority = 0;
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static constexpr Priority LowestPriority = 7;
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struct DMAControlRegister : public ComplexBitMap<uint32_t> {
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static constexpr auto OTCEnable = Bit<uint32_t>(27);
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static constexpr auto OTCPriority = BitRange<Priority>::from_to(24, 26);
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__declare_io_type(DPCR, uint32_t,
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static constexpr auto OTCEnable = IOBitSet(27);
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static constexpr auto OTCPriority = IOValueSet::from_to(24, 26);
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static constexpr auto PIOEnable = Bit<uint32_t>(23);
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static constexpr auto PIOPriority = BitRange<Priority>::from_to(20, 22);
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static constexpr auto PIOEnable = IOBitSet(23);
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static constexpr auto PIOPriority = IOValueSet::from_to(20, 22);
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static constexpr auto SPUEnable = Bit<uint32_t>(19);
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static constexpr auto SPUPriority = BitRange<Priority>::from_to(16, 18);
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static constexpr auto SPUEnable = IOBitSet(19);
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static constexpr auto SPUPriority = IOValueSet::from_to(16, 18);
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static constexpr auto CDROMEnable = Bit<uint32_t>(15);
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static constexpr auto CDROMPriority = BitRange<Priority>::from_to(12, 14);
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static constexpr auto CDROMEnable = IOBitSet(15);
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static constexpr auto CDROMPriority = IOValueSet::from_to(12, 14);
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static constexpr auto GPUEnable = Bit<uint32_t>(11);
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static constexpr auto GPUPriority = BitRange<Priority>::from_to(8, 10);
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static constexpr auto GPUEnable = IOBitSet(11);
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static constexpr auto GPUPriority = IOValueSet::from_to(8, 10);
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static constexpr auto MDECoutEnable = Bit<uint32_t>(7);
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static constexpr auto MDECoutPriority = BitRange<Priority>::from_to(4, 6);
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static constexpr auto MDECoutEnable = IOBitSet(7);
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static constexpr auto MDECoutPriority = IOValueSet::from_to(4, 6);
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static constexpr auto MDECinEnable = Bit<uint32_t>(3);
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static constexpr auto MDECinPriority = BitRange<Priority>::from_to(0, 2);
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};
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static constexpr auto MDECinEnable = IOBitSet(3);
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static constexpr auto MDECinPriority = IOValueSet::from_to(0, 2);
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);
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struct DMAInterruptRegister : public ComplexBitMap<uint32_t> {
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static constexpr auto MasterEnable = Bit<uint32_t>(31);
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static constexpr auto Flags = BitRange<uint32_t>::from_to(24, 30);
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static constexpr auto MasterEnableDPCR = Bit<uint32_t>(23);
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static constexpr auto EnableDPCR = BitRange<uint32_t>::from_to(16, 22);
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static constexpr auto ForceIRQ = Bit<uint32_t>(15);
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};
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__declare_io_type(DICR, uint32_t,
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static constexpr auto MasterEnable = IOBitSet(31);
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static constexpr auto Flags = IOValueSet::from_to(24, 30);
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static constexpr auto MasterEnableDPCR = IOBitSet(23);
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static constexpr auto EnableDPCR = IOValueSet::from_to(16, 22);
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static constexpr auto ForceIRQ = IOBitSet(15);
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);
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__declare_io_port_global_struct(Registers, MDECin, 0x1F801080);
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__declare_io_port_global_struct(Registers, MDECout, 0x1F801090);
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__declare_io_port_global_struct(Registers, GPU, 0x1F8010A0);
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__declare_io_port_global_struct(Registers, CDROM, 0x1F8010B0);
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__declare_io_port_global_struct(Registers, SPU, 0x1F8010C0);
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__declare_io_port_global_struct(Registers, PIO, 0x1F8010D0);
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__declare_io_port_global_struct(Registers, OTC, 0x1F8010E0);
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__declare_new_io_port(MDECin, 0x1F801080);
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__declare_new_io_port(MDECout, 0x1F801090);
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__declare_new_io_port(GPU, 0x1F8010A0);
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__declare_new_io_port(CDROM, 0x1F8010B0);
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__declare_new_io_port(SPU, 0x1F8010C0);
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__declare_new_io_port(PIO, 0x1F8010D0);
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__declare_new_io_port(OTC, 0x1F8010E0);
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__declare_io_port_global(DMAControlRegister, DPCR, 0x1F8010F0);
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__declare_io_port_global(DMAInterruptRegister, DICR, 0x1F8010F4);
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__declare_new_io_port(DPCR, 0x1F8010F0);
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__declare_new_io_port(DICR, 0x1F8010F4);
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}
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}
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#endif //!__JABYENGINE_DMA_IO_HPP__
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