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Finish clean-up

This commit is contained in:
Jaby 2023-09-22 20:53:26 +02:00 committed by Jaby
parent d222d65b3f
commit 656a5b9b81
11 changed files with 240 additions and 265 deletions
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103
include/PSX/System/IOPorts/cd_io.hpp
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@ -31,7 +31,7 @@ namespace JabyEngine {
static constexpr uint8_t Max = 0xFF; static constexpr uint8_t Max = 0xFF;
}; };
__new_declare_io_value(Mode, uint8_t) { __declare_io_value(Mode, uint8_t) {
static constexpr auto DoubleSpeed = Bit(7); static constexpr auto DoubleSpeed = Bit(7);
static constexpr auto SingleSpeed = !DoubleSpeed; static constexpr auto SingleSpeed = !DoubleSpeed;
static constexpr auto XADPCM = Bit(6); static constexpr auto XADPCM = Bit(6);
@ -47,7 +47,7 @@ namespace JabyEngine {
} }
}; };
__new_declare_io_value(IndexStatus, uint8_t) { __declare_io_value(IndexStatus, uint8_t) {
static constexpr auto PortIndex = BitRange::from_to(0, 1); static constexpr auto PortIndex = BitRange::from_to(0, 1);
static constexpr auto HasXAFifoData = Bit(2); static constexpr auto HasXAFifoData = Bit(2);
static constexpr auto IsParameterFifoEmpty = Bit(3); static constexpr auto IsParameterFifoEmpty = Bit(3);
@ -57,16 +57,16 @@ namespace JabyEngine {
static constexpr auto IsTransmissionBusy = Bit(7); static constexpr auto IsTransmissionBusy = Bit(7);
}; };
__new_declare_io_value(InterruptEnable, uint8_t) { __declare_io_value(InterruptEnable, uint8_t) {
static constexpr auto InterruptTypValue = BitRange::from_to(0, 2); static constexpr auto InterruptTypValue = BitRange::from_to(0, 2);
static constexpr auto InterruptExtended = BitRange::from_to(0, 4); static constexpr auto InterruptExtended = BitRange::from_to(0, 4);
static constexpr auto UnknownIRQ = Bit(3); static constexpr auto UnknownIRQ = Bit(3);
static constexpr auto CommandStartIRQ = Bit(4); static constexpr auto CommandStartIRQ = Bit(4);
}; };
using InterruptFlag = InterruptEnable; typedef InterruptEnable InterruptFlag;
__new_declare_io_value(Request, uint8_t) { __declare_io_value(Request, uint8_t) {
static constexpr auto WantCommandStartIRQ = Bit(5); static constexpr auto WantCommandStartIRQ = Bit(5);
static constexpr auto WantData = Bit(7); static constexpr auto WantData = Bit(7);
@ -79,7 +79,7 @@ namespace JabyEngine {
} }
}; };
__new_declare_io_value(SoundMapCoding, uint8_t) { __declare_io_value(SoundMapCoding, uint8_t) {
static constexpr auto Stereo = Bit(0); static constexpr auto Stereo = Bit(0);
static constexpr auto Mono = !Stereo; static constexpr auto Mono = !Stereo;
static constexpr auto SampleRate_18900hz = Bit(2); static constexpr auto SampleRate_18900hz = Bit(2);
@ -89,30 +89,30 @@ namespace JabyEngine {
static constexpr auto Emphasis = Bit(6); static constexpr auto Emphasis = Bit(6);
}; };
__new_declare_io_value(AudioVolumeApply, uint8_t) { __declare_io_value(AudioVolumeApply, uint8_t) {
static constexpr auto Mute = Bit(0); static constexpr auto Mute = Bit(0);
static constexpr auto ApplyChanges = Bit(5); static constexpr auto ApplyChanges = Bit(5);
}; };
__new_declare_io_value(ResponseFifo, uint8_t) { __declare_io_value(ResponseFifo, uint8_t) {
}; };
__new_declare_io_value(CommandFifo, uint8_t) { __declare_io_value(CommandFifo, uint8_t) {
}; };
__new_declare_io_value(DataFifo, uint8_t) { __declare_io_value(DataFifo, uint8_t) {
}; };
__new_declare_io_value(DataFifo16, uint16_t) { __declare_io_value(DataFifo16, uint16_t) {
}; };
__new_declare_io_value(ParameterFifo, uint8_t) { __declare_io_value(ParameterFifo, uint8_t) {
}; };
__new_declare_io_value(SoundMapDataOut, uint8_t) { __declare_io_value(SoundMapDataOut, uint8_t) {
}; };
__new_declare_io_value(LeftCD2LeftSPU, CDDAVolume::Type) { __declare_io_value(LeftCD2LeftSPU, CDDAVolume::Type) {
}; };
__new_declare_io_value(LeftCD2RightSPU, CDDAVolume::Type) { __declare_io_value(LeftCD2RightSPU, CDDAVolume::Type) {
}; };
__new_declare_io_value(RightCD2RightSPU, CDDAVolume::Type) { __declare_io_value(RightCD2RightSPU, CDDAVolume::Type) {
}; };
__new_declare_io_value(RightCD2LeftSPU, CDDAVolume::Type) { __declare_io_value(RightCD2LeftSPU, CDDAVolume::Type) {
}; };
struct Interrupt { struct Interrupt {
@ -125,23 +125,23 @@ namespace JabyEngine {
DiskError = 5 DiskError = 5
}; };
static void enable(New::IOPort<InterruptEnable>& port) { static void enable(IOPort<InterruptEnable>& port) {
port.write(port.read().set2(InterruptEnable::InterruptTypValue.range_max<uint8_t>())); port.write(port.read().set2(InterruptEnable::InterruptTypValue.range_max<uint8_t>()));
} }
static void enable_extended(New::IOPort<InterruptEnable>& port) { static void enable_extended(IOPort<InterruptEnable>& port) {
port.write(InterruptEnable::from(InterruptEnable::InterruptTypValue.range_max<uint8_t>(), InterruptEnable::UnknownIRQ, InterruptEnable::CommandStartIRQ)); port.write(InterruptEnable::from(InterruptEnable::InterruptTypValue.range_max<uint8_t>(), InterruptEnable::UnknownIRQ, InterruptEnable::CommandStartIRQ));
} }
static Type get_type(const New::IOPort<InterruptFlag>& port) { static Type get_type(const IOPort<InterruptFlag>& port) {
return static_cast<Type>(port.read().get2(InterruptFlag::InterruptTypValue)); return static_cast<Type>(port.read().get2(InterruptFlag::InterruptTypValue));
} }
static void ack(New::IOPort<InterruptFlag>& port) { static void ack(IOPort<InterruptFlag>& port) {
port.write(port.read().set2(InterruptFlag::InterruptTypValue.range_max<uint8_t>())); port.write(port.read().set2(InterruptFlag::InterruptTypValue.range_max<uint8_t>()));
} }
static void ack_extended(New::IOPort<InterruptFlag>& port) { static void ack_extended(IOPort<InterruptFlag>& port) {
port.write(InterruptFlag::from(InterruptFlag::InterruptTypValue.range_max<uint8_t>(), InterruptEnable::UnknownIRQ, InterruptEnable::CommandStartIRQ)); port.write(InterruptFlag::from(InterruptFlag::InterruptTypValue.range_max<uint8_t>(), InterruptEnable::UnknownIRQ, InterruptEnable::CommandStartIRQ));
} }
}; };
@ -164,21 +164,18 @@ namespace JabyEngine {
static constexpr auto IORegister2Adr = 0x1F801802; static constexpr auto IORegister2Adr = 0x1F801802;
static constexpr auto IORegister3Adr = 0x1F801803; static constexpr auto IORegister3Adr = 0x1F801803;
__new_declare_io_port(, IndexStatus, 0x1F801800); __declare_io_port(, IndexStatus, 0x1F801800);
//#define __declare_index_io_port(type, name, adr) __cast_io_adr_with_type(inline, type, name, adr)
//#define __declare_index_io_port_const(type, name, adr) __cast_io_adr_with_type(const inline, type, name, adr)
struct PortIndex0 { struct PortIndex0 {
__new_declare_io_port(inline const, ResponseFifo, IORegister1Adr); __declare_io_port(inline const, ResponseFifo, IORegister1Adr);
__new_declare_io_port(inline, CommandFifo, IORegister1Adr); __declare_io_port(inline, CommandFifo, IORegister1Adr);
__new_declare_io_port(inline const, DataFifo, IORegister2Adr); __declare_io_port(inline const, DataFifo, IORegister2Adr);
__new_declare_io_port(inline const, DataFifo16, IORegister2Adr); __declare_io_port(inline const, DataFifo16, IORegister2Adr);
__new_declare_io_port(inline, ParameterFifo, IORegister2Adr); __declare_io_port(inline, ParameterFifo, IORegister2Adr);
__new_declare_io_port(inline const, InterruptEnable, IORegister3Adr); __declare_io_port(inline const, InterruptEnable, IORegister3Adr);
__new_declare_io_port(inline, Request, IORegister3Adr); __declare_io_port(inline, Request, IORegister3Adr);
static void change_to() { static void change_to() {
IndexStatus.write({Index::Index0}); IndexStatus.write({Index::Index0});
@ -186,14 +183,14 @@ namespace JabyEngine {
}; };
struct PortIndex1 { struct PortIndex1 {
__new_declare_io_port(inline const, ResponseFifo, IORegister1Adr); __declare_io_port(inline const, ResponseFifo, IORegister1Adr);
__new_declare_io_port(inline, SoundMapDataOut, IORegister1Adr); __declare_io_port(inline, SoundMapDataOut, IORegister1Adr);
__new_declare_io_port(inline const, DataFifo, IORegister2Adr); __declare_io_port(inline const, DataFifo, IORegister2Adr);
__new_declare_io_port(inline const, DataFifo16, IORegister2Adr); __declare_io_port(inline const, DataFifo16, IORegister2Adr);
__new_declare_io_port(inline, InterruptEnable, IORegister2Adr); __declare_io_port(inline, InterruptEnable, IORegister2Adr);
__new_declare_io_port_w_type(inline, struct InterruptEnable, InterruptFlag, IORegister3Adr); __declare_io_port_w_type(inline, struct InterruptEnable, InterruptFlag, IORegister3Adr);
static void change_to() { static void change_to() {
IndexStatus.write({Index::Index1}); IndexStatus.write({Index::Index1});
@ -201,15 +198,15 @@ namespace JabyEngine {
}; };
struct PortIndex2 { struct PortIndex2 {
__new_declare_io_port(inline const, ResponseFifo, IORegister1Adr); __declare_io_port(inline const, ResponseFifo, IORegister1Adr);
__new_declare_io_port(inline, SoundMapCoding, IORegister1Adr); __declare_io_port(inline, SoundMapCoding, IORegister1Adr);
__new_declare_io_port(inline const, DataFifo, IORegister2Adr); __declare_io_port(inline const, DataFifo, IORegister2Adr);
__new_declare_io_port(inline const, DataFifo16, IORegister2Adr); __declare_io_port(inline const, DataFifo16, IORegister2Adr);
__new_declare_io_port(inline, LeftCD2LeftSPU, IORegister2Adr); __declare_io_port(inline, LeftCD2LeftSPU, IORegister2Adr);
__new_declare_io_port(inline const, InterruptEnable, IORegister3Adr); __declare_io_port(inline const, InterruptEnable, IORegister3Adr);
__new_declare_io_port(inline, LeftCD2RightSPU, IORegister3Adr); __declare_io_port(inline, LeftCD2RightSPU, IORegister3Adr);
static void change_to() { static void change_to() {
IndexStatus.write({Index::Index2}); IndexStatus.write({Index::Index2});
@ -217,15 +214,15 @@ namespace JabyEngine {
}; };
struct PortIndex3 { struct PortIndex3 {
__new_declare_io_port(inline const, ResponseFifo, IORegister1Adr); __declare_io_port(inline const, ResponseFifo, IORegister1Adr);
__new_declare_io_port(inline, RightCD2RightSPU, IORegister1Adr); __declare_io_port(inline, RightCD2RightSPU, IORegister1Adr);
__new_declare_io_port(inline const, DataFifo, IORegister2Adr); __declare_io_port(inline const, DataFifo, IORegister2Adr);
__new_declare_io_port(inline const, DataFifo16, IORegister2Adr); __declare_io_port(inline const, DataFifo16, IORegister2Adr);
__new_declare_io_port(inline, RightCD2LeftSPU, IORegister1Adr); __declare_io_port(inline, RightCD2LeftSPU, IORegister1Adr);
__new_declare_io_port_w_type(inline const, struct InterruptEnable, InterruptFlag, IORegister3Adr); __declare_io_port_w_type(inline const, struct InterruptEnable, InterruptFlag, IORegister3Adr);
__new_declare_io_port(inline, AudioVolumeApply, IORegister3Adr); __declare_io_port( inline, AudioVolumeApply, IORegister3Adr);
static void change_to() { static void change_to() {
IndexStatus.write({Index::Index3}); IndexStatus.write({Index::Index3});

34
include/PSX/System/IOPorts/dma_io.hpp
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@ -4,11 +4,11 @@
namespace JabyEngine { namespace JabyEngine {
namespace DMA_IO { namespace DMA_IO {
__new_declare_io_value(MADR, uint32_t) { __declare_io_value(MADR, uint32_t) {
static constexpr auto MemoryAdr = BitRange::from_to(0, 23); static constexpr auto MemoryAdr = BitRange::from_to(0, 23);
}; };
__new_declare_io_value(BCR, uint32_t) { __declare_io_value(BCR, uint32_t) {
struct SyncMode0 { struct SyncMode0 {
static constexpr auto NumberOfWords = BitRange::from_to(0, 15); static constexpr auto NumberOfWords = BitRange::from_to(0, 15);
static constexpr auto CD_OneBlock = Bit(16); static constexpr auto CD_OneBlock = Bit(16);
@ -31,7 +31,7 @@ namespace JabyEngine {
}; };
}; };
__new_declare_io_value(CHCHR, uint32_t) { __declare_io_value(CHCHR, uint32_t) {
enum SyncMode_t { enum SyncMode_t {
Sync0 = 0, //Start immediately, Sync0 = 0, //Start immediately,
Sync1 = 1, //Sync blocks to DMA requests Sync1 = 1, //Sync blocks to DMA requests
@ -90,9 +90,9 @@ namespace JabyEngine {
#pragma pack(push, 1) #pragma pack(push, 1)
struct Registers { struct Registers {
New::IOPort<MADR> adr; IOPort<MADR> adr;
New::IOPort<BCR> block_ctrl; IOPort<BCR> block_ctrl;
New::IOPort<CHCHR> channel_ctrl; IOPort<CHCHR> channel_ctrl;
inline void set_adr(uintptr_t adr) { inline void set_adr(uintptr_t adr) {
this->adr.write({bit::value::set_normalized(0u, MADR::MemoryAdr.with(adr))}); this->adr.write({bit::value::set_normalized(0u, MADR::MemoryAdr.with(adr))});
@ -109,7 +109,7 @@ namespace JabyEngine {
static constexpr Priority HighestPriority = 0; static constexpr Priority HighestPriority = 0;
static constexpr Priority LowestPriority = 7; static constexpr Priority LowestPriority = 7;
__new_declare_io_value(DPCR, uint32_t) { __declare_io_value(DPCR, uint32_t) {
static constexpr auto OTCEnable = Bit(27); static constexpr auto OTCEnable = Bit(27);
static constexpr auto OTCPriority = BitRange::from_to(24, 26); static constexpr auto OTCPriority = BitRange::from_to(24, 26);
@ -132,7 +132,7 @@ namespace JabyEngine {
static constexpr auto MDECinPriority = BitRange::from_to(0, 2); static constexpr auto MDECinPriority = BitRange::from_to(0, 2);
}; };
__new_declare_io_value(DICR, uint32_t) { __declare_io_value(DICR, uint32_t) {
static constexpr auto MasterEnable = Bit(31); static constexpr auto MasterEnable = Bit(31);
static constexpr auto Flags = BitRange::from_to(24, 30); static constexpr auto Flags = BitRange::from_to(24, 30);
static constexpr auto MasterEnableDPCR = Bit(23); static constexpr auto MasterEnableDPCR = Bit(23);
@ -140,16 +140,16 @@ namespace JabyEngine {
static constexpr auto ForceIRQ = Bit(15); static constexpr auto ForceIRQ = Bit(15);
}; };
__new_declare_value_at(, Registers, MDECin, 0x1F801080); __declare_value_at(, Registers, MDECin, 0x1F801080);
__new_declare_value_at(, Registers, MDECout, 0x1F801090); __declare_value_at(, Registers, MDECout, 0x1F801090);
__new_declare_value_at(, Registers, GPU, 0x1F8010A0); __declare_value_at(, Registers, GPU, 0x1F8010A0);
__new_declare_value_at(, Registers, CDROM, 0x1F8010B0); __declare_value_at(, Registers, CDROM, 0x1F8010B0);
__new_declare_value_at(, Registers, SPU, 0x1F8010C0); __declare_value_at(, Registers, SPU, 0x1F8010C0);
__new_declare_value_at(, Registers, PIO, 0x1F8010D0); __declare_value_at(, Registers, PIO, 0x1F8010D0);
__new_declare_value_at(, Registers, OTC, 0x1F8010E0); __declare_value_at(, Registers, OTC, 0x1F8010E0);
__new_declare_io_port(, DPCR, 0x1F8010F0); __declare_io_port(, DPCR, 0x1F8010F0);
__new_declare_io_port(, DICR, 0x1F8010F4); __declare_io_port(, DICR, 0x1F8010F4);
} }
} }
#endif //!__JABYENGINE_DMA_IO_HPP__ #endif //!__JABYENGINE_DMA_IO_HPP__

18
include/PSX/System/IOPorts/gpu_io.hpp
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@ -35,7 +35,7 @@ namespace JabyEngine {
Off = 1 Off = 1
}; };
__new_declare_io_value(DisplayMode, uint32_t) { __declare_io_value(DisplayMode, uint32_t) {
enum struct TVEncoding { enum struct TVEncoding {
NTSC = 0, NTSC = 0,
PAL = 1, PAL = 1,
@ -67,12 +67,12 @@ namespace JabyEngine {
} }
}; };
__new_declare_io_value(GP0, uint32_t) { __declare_io_value(GP0, uint32_t) {
static constexpr auto ID = BitRange::from_to(24, 31); static constexpr auto ID = BitRange::from_to(24, 31);
static constexpr auto Value = BitRange::from_to(0, 23); static constexpr auto Value = BitRange::from_to(0, 23);
}; };
__new_declare_io_value(GP1, uint32_t) { __declare_io_value(GP1, uint32_t) {
static constexpr auto ID = BitRange::from_to(24, 31); static constexpr auto ID = BitRange::from_to(24, 31);
static constexpr auto Value = BitRange::from_to(0, 23); static constexpr auto Value = BitRange::from_to(0, 23);
}; };
@ -185,10 +185,10 @@ namespace JabyEngine {
} }
}; };
__new_declare_io_value(GPUREAD, uint32_t) { __declare_io_value(GPUREAD, uint32_t) {
}; };
__new_declare_io_value(GPUSTAT, uint32_t) { __declare_io_value(GPUSTAT, uint32_t) {
static constexpr auto DrawingOddLinesInterlaced = Bit(31); static constexpr auto DrawingOddLinesInterlaced = Bit(31);
static constexpr auto DMADirectionValue = BitRange::from_to(29, 30); static constexpr auto DMADirectionValue = BitRange::from_to(29, 30);
static constexpr auto DMAReady = Bit(28); static constexpr auto DMAReady = Bit(28);
@ -217,11 +217,11 @@ namespace JabyEngine {
static constexpr auto TexturePageY256 = Bit(4); static constexpr auto TexturePageY256 = Bit(4);
}; };
__new_declare_io_port(, GP0, 0x1F801810); __declare_io_port(, GP0, 0x1F801810);
__new_declare_io_port(, GP1, 0x1F801814); __declare_io_port(, GP1, 0x1F801814);
__new_declare_io_port(const, GPUREAD, 0x1F801810); __declare_io_port(const, GPUREAD, 0x1F801810);
__new_declare_io_port(const, GPUSTAT, 0x1F801814); __declare_io_port(const, GPUSTAT, 0x1F801814);
} }
} }
#endif //!__JABYENGINE_GPU_IO_HPP__ #endif //!__JABYENGINE_GPU_IO_HPP__

8
include/PSX/System/IOPorts/interrupt_io.hpp
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@ -17,14 +17,14 @@ namespace JabyEngine {
static constexpr auto Controller = Bit(10); static constexpr auto Controller = Bit(10);
static constexpr auto LightPen = Controller; static constexpr auto LightPen = Controller;
__new_declare_io_value(Status, uint32_t) { __declare_io_value(Status, uint32_t) {
}; };
__new_declare_io_value(Mask, uint32_t) { __declare_io_value(Mask, uint32_t) {
}; };
__new_declare_io_port(inline, Status, 0x1F801070); __declare_io_port(inline, Status, 0x1F801070);
__new_declare_io_port(inline, Mask, 0x1F801074); __declare_io_port(inline, Mask, 0x1F801074);
static bool is_irq(Bit irq) { static bool is_irq(Bit irq) {
return Status.read().is_set2(irq); return Status.read().is_set2(irq);

32
include/PSX/System/IOPorts/ioport.hpp
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@ -4,7 +4,15 @@
#include "../../Auxiliary/bits.hpp" #include "../../Auxiliary/bits.hpp"
namespace JabyEngine { namespace JabyEngine {
namespace New { namespace IOAdress {
constexpr uintptr_t patch_adr(uintptr_t adr) {
constexpr uintptr_t Mask = 0xF0000000;
constexpr uintptr_t Base = 0x10000000; // We might want to change this later to 0xB0000000 for caching and stuff (More research needed)
return (Base + (adr & ~Mask));
}
}
namespace internal { namespace internal {
template<typename T, typename S> template<typename T, typename S>
struct IOValue { struct IOValue {
@ -102,21 +110,11 @@ namespace JabyEngine {
} }
}; };
#define __new_declare_io_value(name, type) struct name : public ::JabyEngine::New::internal::IOValue<struct name, type> #define __declare_io_value(name, type) struct name : public ::JabyEngine::internal::IOValue<struct name, type>
#define __new_declare_value_at(cv, type, name, adr) static cv auto& name = *reinterpret_cast<type*>(IOAdress::patch_adr(adr)) #define __declare_value_at(cv, type, name, adr) static cv auto& name = *reinterpret_cast<type*>(::JabyEngine::IOAdress::patch_adr(adr))
#define __new_declare_array_at(cv, type, name, size, adr) static cv auto& name = reinterpret_cast<type(&)[size]>(*reinterpret_cast<type*>(IOAdress::patch_adr(adr))) #define __declare_array_at(cv, type, name, size, adr) static cv auto& name = reinterpret_cast<type(&)[size]>(*reinterpret_cast<type*>(IOAdress::patch_adr(adr)))
#define __new_declare_io_port_w_type(cv, type, name, adr) __new_declare_value_at(cv, ::JabyEngine::New::IOPort<type>, name, adr) #define __declare_io_port_w_type(cv, type, name, adr) __declare_value_at(cv, ::JabyEngine::IOPort<type>, name, adr)
#define __new_declare_io_port(cv, name, adr) __new_declare_io_port_w_type(cv, struct name, name, adr) #define __declare_io_port(cv, name, adr) __declare_io_port_w_type(cv, struct name, name, adr)
#define __new_declare_io_port_array(cv, name, size, adr) __new_declare_array_at(cv, struct name, name, size, adr) #define __declare_io_port_array(cv, name, size, adr) __declare_array_at(cv, struct name, name, size, adr)
}
namespace IOAdress {
constexpr uintptr_t patch_adr(uintptr_t adr) {
constexpr uintptr_t Mask = 0xF0000000;
constexpr uintptr_t Base = 0x10000000; // We might want to change this later to 0xB0000000 for caching and stuff (More research needed)
return (Base + (adr & ~Mask));
}
}
} }
#endif //!__JABYENGINE_IOPORT_HPP__ #endif //!__JABYENGINE_IOPORT_HPP__

8
include/PSX/System/IOPorts/memory_io.hpp
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@ -4,20 +4,20 @@
namespace JabyEngine { namespace JabyEngine {
namespace Memory_IO { namespace Memory_IO {
__new_declare_io_value(COM_DELAY, uint32_t) { __declare_io_value(COM_DELAY, uint32_t) {
static constexpr COM_DELAY create() { static constexpr COM_DELAY create() {
return COM_DELAY{0x1325}; return COM_DELAY{0x1325};
} }
}; };
__new_declare_io_value(CD_DELAY, uint32_t) { __declare_io_value(CD_DELAY, uint32_t) {
static constexpr CD_DELAY create() { static constexpr CD_DELAY create() {
return CD_DELAY{0x20943}; return CD_DELAY{0x20943};
} }
}; };
__new_declare_io_port(, COM_DELAY, 0x1F801020); __declare_io_port(, COM_DELAY, 0x1F801020);
__new_declare_io_port(, CD_DELAY, 0x1F801018); __declare_io_port(, CD_DELAY, 0x1F801018);
} }
} }

74
include/PSX/System/IOPorts/spu_io.hpp
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@ -25,18 +25,18 @@ namespace JabyEngine {
//0..3 = +7, +6, +5, +4 or -6, -7, -6, -5 //0..3 = +7, +6, +5, +4 or -6, -7, -6, -5
typedef uint8_t Step; typedef uint8_t Step;
__new_declare_io_value(DataTransferControl, uint16_t) { __declare_io_value(DataTransferControl, uint16_t) {
}; };
__new_declare_io_value(SimpleVolume, int16_t) { __declare_io_value(SimpleVolume, int16_t) {
constexpr operator int16_t() const { constexpr operator int16_t() const {
return this->raw; return this->raw;
} }
}; };
__new_declare_io_value(Adr, uint16_t) { __declare_io_value(Adr, uint16_t) {
}; };
__new_declare_io_value(SampleRate, uint16_t) { __declare_io_value(SampleRate, uint16_t) {
static constexpr SampleRate from_HZ(double freq) { static constexpr SampleRate from_HZ(double freq) {
//4096 == 44100Hz //4096 == 44100Hz
constexpr double Base = (4096.0 / 44100.0); constexpr double Base = (4096.0 / 44100.0);
@ -45,7 +45,7 @@ namespace JabyEngine {
} }
}; };
__new_declare_io_value(SweepVolume, int16_t) { __declare_io_value(SweepVolume, int16_t) {
// For Volume Mode // For Volume Mode
static constexpr auto SweepEnable = Bit(15); static constexpr auto SweepEnable = Bit(15);
static constexpr auto VolumeEnable = !SweepEnable; static constexpr auto VolumeEnable = !SweepEnable;
@ -59,7 +59,7 @@ namespace JabyEngine {
static constexpr auto SweepStep = BitRange::from_to(0, 1); static constexpr auto SweepStep = BitRange::from_to(0, 1);
}; };
__new_declare_io_value(SR, uint16_t) { __declare_io_value(SR, uint16_t) {
static constexpr auto SustainMode = Bit(31 - 16); static constexpr auto SustainMode = Bit(31 - 16);
static constexpr auto SustainDirection = Bit(30 - 16); static constexpr auto SustainDirection = Bit(30 - 16);
static constexpr auto SustainShift = BitRange::from_to((24 - 16), (28 - 16)); static constexpr auto SustainShift = BitRange::from_to((24 - 16), (28 - 16));
@ -68,7 +68,7 @@ namespace JabyEngine {
static constexpr auto ReleaseShift = BitRange::from_to((16 - 16), (20 - 16)); static constexpr auto ReleaseShift = BitRange::from_to((16 - 16), (20 - 16));
}; };
__new_declare_io_value(AD, uint16_t) { __declare_io_value(AD, uint16_t) {
static constexpr auto AttackMode = Bit(15); static constexpr auto AttackMode = Bit(15);
static constexpr auto AttackShift = BitRange::from_to(10, 14); static constexpr auto AttackShift = BitRange::from_to(10, 14);
static constexpr auto AttackStep = BitRange::from_to(8, 9); static constexpr auto AttackStep = BitRange::from_to(8, 9);
@ -78,14 +78,14 @@ namespace JabyEngine {
#pragma pack(push, 1) #pragma pack(push, 1)
struct Voice { struct Voice {
New::IOPort<SweepVolume> volumeLeft; //Offset: 0x0 IOPort<SweepVolume> volumeLeft; //Offset: 0x0
New::IOPort<SweepVolume> volumeRight; //Offset: 0x2 IOPort<SweepVolume> volumeRight; //Offset: 0x2
New::IOPort<SampleRate> sampleRate; //Offset: 0x4; IOPort<SampleRate> sampleRate; //Offset: 0x4;
New::IOPort<Adr> adr; //Offset: 0x6 IOPort<Adr> adr; //Offset: 0x6
New::IOPort<AD> ad; //Offset: 0x8 IOPort<AD> ad; //Offset: 0x8
New::IOPort<SR> sr; //Offset: 0xA IOPort<SR> sr; //Offset: 0xA
New::IOPort<SimpleVolume> currentVolume; //Offset: 0xC IOPort<SimpleVolume> currentVolume; //Offset: 0xC
New::IOPort<Adr> repeatAdr; //Offset: 0xE IOPort<Adr> repeatAdr; //Offset: 0xE
static constexpr Adr start_adr() { static constexpr Adr start_adr() {
return {0x200}; return {0x200};
@ -93,7 +93,7 @@ namespace JabyEngine {
}; };
#pragma pack(pop) #pragma pack(pop)
__new_declare_io_value(ControlRegister, uint16_t) { __declare_io_value(ControlRegister, uint16_t) {
enum RAMTransferMode { enum RAMTransferMode {
Stop = 0, Stop = 0,
ManualWrite = 1, ManualWrite = 1,
@ -114,56 +114,56 @@ namespace JabyEngine {
static constexpr auto CDAudioEnable = Bit(0); static constexpr auto CDAudioEnable = Bit(0);
}; };
__new_declare_io_value(PMON, uint16_t) { __declare_io_value(PMON, uint16_t) {
static constexpr auto EnableBits = BitRange::from_to(1, 23); static constexpr auto EnableBits = BitRange::from_to(1, 23);
}; };
__new_declare_io_value(NON, uint16_t) { __declare_io_value(NON, uint16_t) {
static constexpr auto NoiseBits = BitRange::from_to(0, 23); static constexpr auto NoiseBits = BitRange::from_to(0, 23);
}; };
__new_declare_io_value(EON, uint16_t) { __declare_io_value(EON, uint16_t) {
static constexpr auto EchoBits = BitRange::from_to(0, 23); static constexpr auto EchoBits = BitRange::from_to(0, 23);
}; };
static constexpr size_t VoiceCount = 24; static constexpr size_t VoiceCount = 24;
struct Key { struct Key {
__new_declare_io_port_w_type(inline, New::ubus32_t, On, 0x1F801D88); __declare_io_port_w_type(inline, ubus32_t, On, 0x1F801D88);
__new_declare_io_port_w_type(inline, New::ubus32_t, Off, 0x1F801D8C); __declare_io_port_w_type(inline, ubus32_t, Off, 0x1F801D8C);
__new_declare_io_port_w_type(inline, New::ubus32_t, Status, 0x1F801D9C); __declare_io_port_w_type(inline, ubus32_t, Status, 0x1F801D9C);
}; };
struct MainVolume { struct MainVolume {
__new_declare_io_port_w_type(inline, SweepVolume, Left, 0x1F801D80); __declare_io_port_w_type(inline, SweepVolume, Left, 0x1F801D80);
__new_declare_io_port_w_type(inline, SweepVolume, Right, 0x1F801D82); __declare_io_port_w_type(inline, SweepVolume, Right, 0x1F801D82);
}; };
struct CDVolume { struct CDVolume {
__new_declare_io_port_w_type(inline, SimpleVolume, Left, 0x1F801DB0); __declare_io_port_w_type(inline, SimpleVolume, Left, 0x1F801DB0);
__new_declare_io_port_w_type(inline, SimpleVolume, Right, 0x1F801DB2); __declare_io_port_w_type(inline, SimpleVolume, Right, 0x1F801DB2);
}; };
struct ExternalAudioInputVolume { struct ExternalAudioInputVolume {
__new_declare_io_port_w_type(inline, SimpleVolume, Left, 0x1F801DB4); __declare_io_port_w_type(inline, SimpleVolume, Left, 0x1F801DB4);
__new_declare_io_port_w_type(inline, SimpleVolume, Right, 0x1F801DB6); __declare_io_port_w_type(inline, SimpleVolume, Right, 0x1F801DB6);
}; };
struct Reverb { struct Reverb {
struct Volume { struct Volume {
__new_declare_io_port_w_type(inline, SimpleVolume, Left, 0x1F801D84); __declare_io_port_w_type(inline, SimpleVolume, Left, 0x1F801D84);
__new_declare_io_port_w_type(inline, SimpleVolume, Right, 0x1F801D86); __declare_io_port_w_type(inline, SimpleVolume, Right, 0x1F801D86);
}; };
__new_declare_io_port_w_type(inline, Adr, WorkAreaAdr, 0x1F801DA2); __declare_io_port_w_type(inline, Adr, WorkAreaAdr, 0x1F801DA2);
}; };
__new_declare_io_port(, ControlRegister, 0x1F801DAA); __declare_io_port(, ControlRegister, 0x1F801DAA);
__new_declare_io_port(, DataTransferControl, 0x1F801DAC); __declare_io_port(, DataTransferControl, 0x1F801DAC);
__new_declare_io_port(, PMON, 0x1F801D90); __declare_io_port(, PMON, 0x1F801D90);
__new_declare_io_port(, NON, 0x1F801D94); __declare_io_port(, NON, 0x1F801D94);
__new_declare_io_port(, EON, 0x1F801D98); __declare_io_port(, EON, 0x1F801D98);
__new_declare_io_port_array(, Voice, VoiceCount, 0x1F801C00); __declare_io_port_array(, Voice, VoiceCount, 0x1F801C00);
} }
} }
#endif //!__JABYENGINE_SPU_IO_HPP__ #endif //!__JABYENGINE_SPU_IO_HPP__

18
include/PSX/System/IOPorts/timer_io.hpp
View File

@ -4,7 +4,7 @@
namespace JabyEngine { namespace JabyEngine {
namespace Timer_IO { namespace Timer_IO {
__new_declare_io_value(CounterMode, uint32_t) { __declare_io_value(CounterMode, uint32_t) {
static constexpr auto SyncEnable = Bit(0); static constexpr auto SyncEnable = Bit(0);
static constexpr auto FreeRun = !SyncEnable; static constexpr auto FreeRun = !SyncEnable;
static constexpr auto SyncMode = BitRange::from_to(1, 2); static constexpr auto SyncMode = BitRange::from_to(1, 2);
@ -21,19 +21,19 @@ namespace JabyEngine {
static constexpr auto IsMaxReached = Bit(12); static constexpr auto IsMaxReached = Bit(12);
}; };
__new_declare_io_value(CounterTarget, uint32_t) { __declare_io_value(CounterTarget, uint32_t) {
static constexpr auto CounterTargetValue = BitRange::from_to(0, 15); static constexpr auto CounterTargetValue = BitRange::from_to(0, 15);
}; };
__new_declare_io_value(CounterValue, uint32_t) { __declare_io_value(CounterValue, uint32_t) {
static constexpr auto Value = BitRange::from_to(0, 15); static constexpr auto Value = BitRange::from_to(0, 15);
}; };
#pragma pack(push, 1) #pragma pack(push, 1)
struct Counter { struct Counter {
New::IOPort<CounterValue> value; IOPort<CounterValue> value;
New::IOPort<CounterMode> mode; IOPort<CounterMode> mode;
New::IOPort<CounterTarget> target; IOPort<CounterTarget> target;
private: private:
uint32_t _unused; uint32_t _unused;
@ -107,9 +107,9 @@ namespace JabyEngine {
}; };
#pragma pack(pop) #pragma pack(pop)
__new_declare_value_at(, struct Counter0, Counter0, counter_base_adr(0)); __declare_value_at(, struct Counter0, Counter0, counter_base_adr(0));
__new_declare_value_at(, struct Counter1, Counter1, counter_base_adr(1)); __declare_value_at(, struct Counter1, Counter1, counter_base_adr(1));
__new_declare_value_at(, struct Counter2, Counter2, counter_base_adr(2)); __declare_value_at(, struct Counter2, Counter2, counter_base_adr(2));
} }
} }

6
src/Library/internal-include/CD/cd_internal.hpp
View File

@ -15,11 +15,11 @@ namespace JabyEngine {
} }
template<typename...ARGS> template<typename...ARGS>
static void send(New::IOPort<CD_IO::CommandFifo>& cmd_fifo, New::IOPort<CD_IO::ParameterFifo>& parameter_fifo, CD_IO::Command::Desc cmd, ARGS...args) { static void send(IOPort<CD_IO::CommandFifo>& cmd_fifo, IOPort<CD_IO::ParameterFifo>& parameter_fifo, CD_IO::Command::Desc cmd, ARGS...args) {
while(CD_IO::IndexStatus.read().is_set2(CD_IO::IndexStatus::IsTransmissionBusy)); while(CD_IO::IndexStatus.read().is_set2(CD_IO::IndexStatus::IsTransmissionBusy));
((parameter_fifo.write(CD_IO::ParameterFifo{args})),...); ((parameter_fifo.write(CD_IO::ParameterFifo{args})),...);
cmd_fifo.write(CD_IO::CommandFifo{cmd.id}); cmd_fifo.write(CD_IO::CommandFifo {cmd.id});
cmd_interrupt_bit = bit::set(0, cmd.complete_irq); cmd_interrupt_bit = bit::set(0, cmd.complete_irq);
} }
@ -29,7 +29,7 @@ namespace JabyEngine {
} }
template<typename...ARGS> template<typename...ARGS>
static void send_wait(New::IOPort<CD_IO::CommandFifo>& cmd_fifo, New::IOPort<CD_IO::ParameterFifo>& parameter_fifo, CD_IO::Command::Desc cmd, ARGS...args) { static void send_wait(IOPort<CD_IO::CommandFifo>& cmd_fifo, IOPort<CD_IO::ParameterFifo>& parameter_fifo, CD_IO::Command::Desc cmd, ARGS...args) {
send(cmd_fifo, parameter_fifo, cmd, args...); send(cmd_fifo, parameter_fifo, cmd, args...);
wait_completed(); wait_completed();
} }

6
src/Library/src/BootLoader/gpu_boot.cpp
View File

@ -26,7 +26,7 @@ namespace JabyEngine {
static void configurate_display() { static void configurate_display() {
// Ideal I hope that an offset of 0,0 will produce a well enough centered picture for every TV // Ideal I hope that an offset of 0,0 will produce a well enough centered picture for every TV
GPU_IO::GP1.write(GPU_IO::Command::DisplayMode(internal::Display::DisplayMode)); GPU_IO::GP1.write(GPU_IO::Command::DisplayMode(::JabyEngine::GPU::internal::Display::DisplayMode));
GPU::Display::set_offset(0, 0); GPU::Display::set_offset(0, 0);
} }
@ -59,7 +59,7 @@ namespace JabyEngine {
state.process(bytes_ready); state.process(bytes_ready);
// Duplicate DisplayBuffer content // Duplicate DisplayBuffer content
internal::copy_vram_to_vram({PositionU16(0, Display::Height), SizeU16(Display::Width, Display::Height)}, PositionU16(0, 0)); ::JabyEngine::GPU::internal::copy_vram_to_vram({PositionU16(0, Display::Height), SizeU16(Display::Width, Display::Height)}, PositionU16(0, 0));
Display::enable(); Display::enable();
} }
@ -67,7 +67,7 @@ namespace JabyEngine {
void setup() { void setup() {
GPU_IO::GP1.write(GPU_IO::Command::Reset()); GPU_IO::GP1.write(GPU_IO::Command::Reset());
configurate_display(); configurate_display();
internal::Display::exchange_buffer_and_display(); ::JabyEngine::GPU::internal::Display::exchange_buffer_and_display();
GPU::internal::wait_ready_for_CMD(); GPU::internal::wait_ready_for_CMD();
GPU::internal::quick_fill_fast(Color24::Black(), {PositionU16(0, 0), SizeU16(Display::Width, Display::Height)}); GPU::internal::quick_fill_fast(Color24::Black(), {PositionU16(0, 0), SizeU16(Display::Width, Display::Height)});

20
src/Library/src/BootLoader/start_boot.cpp
View File

@ -11,30 +11,10 @@ extern "C" uint32_t __planschi_start;
extern "C" uint32_t __planschi_end; extern "C" uint32_t __planschi_end;
namespace JabyEngine { namespace JabyEngine {
// For now
namespace Blubb {
__new_declare_io_value(Test, uint32_t) {
};
__new_declare_io_port(, Test, 0);
static void bla(New::IOPort<struct Test>& wuff) {
asm("#planschi");
const auto a = Test::from(Bit(1), Bit(2));
wuff.write(a);
wuff.write(a);
wuff.write(a);
asm("#planschi");
}
}
namespace boot { namespace boot {
namespace Start { namespace Start {
static void enable_DMA() { static void enable_DMA() {
::JabyEngine::Blubb::bla(::JabyEngine::Blubb::Test);
asm("#miau");
DMA_IO::DPCR.write(DMA_IO::DPCR.read().set2(DMA_IO::DPCR::SPUEnable, DMA_IO::DPCR::GPUEnable, DMA_IO::DPCR::CDROMEnable)); DMA_IO::DPCR.write(DMA_IO::DPCR.read().set2(DMA_IO::DPCR::SPUEnable, DMA_IO::DPCR::GPUEnable, DMA_IO::DPCR::CDROMEnable));
asm("#miau");
} }
static void setup() { static void setup() {