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Update IOPort code and prepare DMA usage - needs all testing

This commit is contained in:
Björn Gaier 2024-09-06 18:58:36 +01:00
parent e7b9033f52
commit 7b99fd4de8
6 changed files with 14 additions and 41 deletions
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4
include/PSX/System/IOPorts/IOValues/spu_io_values.hpp
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@ -23,7 +23,7 @@ namespace JabyEngine {
static constexpr auto ExternalAudioEnable = Bit(1); static constexpr auto ExternalAudioEnable = Bit(1);
static constexpr auto CDAudioEnable = Bit(0); static constexpr auto CDAudioEnable = Bit(0);
}; };
using SRAM_Adr = uint16_t; __declare_io_value(SRAM_Adr, uint16_t) {};
} }
} }

29
include/PSX/System/IOPorts/ioport.hpp
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@ -74,41 +74,16 @@ namespace JabyEngine {
} }
}; };
template<typename S, typename T = S::UnderlyingType>
struct IOPortX {
using Value = S;
S read() const {
return S{*const_cast<const volatile T*>(reinterpret_cast<const T*>(this))};
}
void write(S value) {
*const_cast<volatile T*>(reinterpret_cast<T*>(this)) = value.raw;
}
};
template<typename T>
struct IOPortX<T, T> {
T read() const {
return *const_cast<const volatile T*>(reinterpret_cast<const T*>(this));
}
void write(T value) {
*const_cast<volatile T*>(reinterpret_cast<T*>(this)) = value;
}
};
template<typename T> template<typename T>
struct IOPort { struct IOPort {
using Value = T; using Value = T;
T value;
T read() const { T read() const {
return {const_cast<const volatile IOPort<T>*>(this)->value.raw}; return {const_cast<const volatile Value*>(reinterpret_cast<const Value*>(this))->raw};
} }
void write(T value) { void write(T value) {
const_cast<volatile IOPort<T>*>(this)->value.raw = value.raw; const_cast<volatile Value*>(reinterpret_cast<Value*>(this))->raw = value.raw;
} }
}; };

14
include/PSX/System/IOPorts/spu_io.hpp
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@ -42,8 +42,6 @@ namespace JabyEngine {
return this->raw; return this->raw;
} }
}; };
__declare_io_value(Adr, uint16_t) {
};
__declare_io_value(SampleRate, uint16_t) { __declare_io_value(SampleRate, uint16_t) {
static constexpr SampleRate from_HZ(uint32_t freq) { static constexpr SampleRate from_HZ(uint32_t freq) {
@ -94,13 +92,13 @@ namespace JabyEngine {
IOPort<SweepVolume> volumeLeft; //Offset: 0x0 IOPort<SweepVolume> volumeLeft; //Offset: 0x0
IOPort<SweepVolume> volumeRight; //Offset: 0x2 IOPort<SweepVolume> volumeRight; //Offset: 0x2
IOPort<SampleRate> sampleRate; //Offset: 0x4; IOPort<SampleRate> sampleRate; //Offset: 0x4;
IOPort<Adr> adr; //Offset: 0x6 IOPort<SRAM_Adr> adr; //Offset: 0x6
IOPort<AD> ad; //Offset: 0x8 IOPort<AD> ad; //Offset: 0x8
IOPort<SR> sr; //Offset: 0xA IOPort<SR> sr; //Offset: 0xA
IOPort<SimpleVolume> currentVolume; //Offset: 0xC IOPort<SimpleVolume> currentVolume; //Offset: 0xC
IOPort<Adr> repeatAdr; //Offset: 0xE IOPort<SRAM_Adr> repeatAdr; //Offset: 0xE
static constexpr Adr start_adr() { static constexpr SRAM_Adr start_adr() {
return {0x200}; return {0x200};
} }
}; };
@ -147,16 +145,16 @@ namespace JabyEngine {
__declare_io_port_w_type(inline, SimpleVolume, Left, 0x1F801D84); __declare_io_port_w_type(inline, SimpleVolume, Left, 0x1F801D84);
__declare_io_port_w_type(inline, SimpleVolume, Right, 0x1F801D86); __declare_io_port_w_type(inline, SimpleVolume, Right, 0x1F801D86);
}; };
__declare_io_port_w_type(inline, Adr, WorkAreaAdr, 0x1F801DA2); __declare_io_port_w_type(inline, SRAM_Adr, WorkAreaAdr, 0x1F801DA2);
}; };
static constexpr SimpleVolume operator""_vol(long double fraction) { static constexpr SimpleVolume operator""_vol(long double fraction) {
return {static_cast<int16_t>(static_cast<long double>(I16_MAX)*fraction)}; return {static_cast<int16_t>(static_cast<long double>(I16_MAX)*fraction)};
} }
struct SRAMTransferAddressIO : public IOPortX<SRAM_Adr, SRAM_Adr> {}; struct SRAMTransferAddressIO : public IOPort<SRAM_Adr> {};
struct ControlRegisterIO : public IOPortX<SPU_IO_Values::ControlRegister> { struct ControlRegisterIO : public IOPort<SPU_IO_Values::ControlRegister> {
using TransferMode = Value::RAMTransferMode; using TransferMode = Value::RAMTransferMode;
void set_transfer_mode(TransferMode mode) { void set_transfer_mode(TransferMode mode) {

2
src/Library/internal-include/SPU/spu_internal.hpp
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@ -21,7 +21,7 @@ namespace JabyEngine {
SPU_IO::ControlRegister.set_transfer_mode(SPU_IO::ControlRegister::DMAWrite); SPU_IO::ControlRegister.set_transfer_mode(SPU_IO::ControlRegister::DMAWrite);
} }
static void set_src(SPU::SRAM_Adr adr) { static void set_src(uintptr_t adr) {
DMA_IO::SPU.set_adr(adr); DMA_IO::SPU.set_adr(adr);
} }

2
src/Library/src/File/Processor/vag_processor.cpp
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@ -41,7 +41,7 @@ namespace JabyEngine {
static Progress parse_sample(State::Configuration& config, VAGState& state) { static Progress parse_sample(State::Configuration& config, VAGState& state) {
// Load balancer? // Load balancer?
return Progress::Error;
} }
static Progress parse_header(State::Configuration& config, VAGState& state) { static Progress parse_header(State::Configuration& config, VAGState& state) {

4
src/Library/src/SPU/spu.cpp
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@ -11,9 +11,9 @@ namespace JabyEngine {
SRAM_Adr Voice :: allocate(size_t size) const { SRAM_Adr Voice :: allocate(size_t size) const {
Voice::stop(); Voice::stop();
const auto voice_id = Voice::get_id(); const auto voice_id = Voice::get_id();
const auto adr = static_cast<SRAM_Adr>(reinterpret_cast<uintptr_t>(SPU_MMU::allocate(voice_id, size))); const auto adr = SRAM_Adr{static_cast<SRAM_Adr::UnderlyingType>(reinterpret_cast<uintptr_t>(SPU_MMU::allocate(voice_id, size)))};
SPU_IO::Voice[voice_id].adr.write({adr}); SPU_IO::Voice[voice_id].adr.write(adr);
return adr; return adr;
} }