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Support DMA with new IO

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This commit is contained in:
jaby
2023-09-17 12:30:43 +02:00
parent 19c5485658
commit 87a7a349cc
6 changed files with 72 additions and 63 deletions
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94
include/PSX/System/IOPorts/dma_io.hpp
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@@ -4,18 +4,18 @@
namespace JabyEngine {
namespace DMA_IO {
__declare_io_type(MADR, uint32_t,
__new_declare_io_value(MADR, uint32_t) {
static constexpr auto MemoryAdr = BitRange::from_to(0, 23);
);
};
__declare_io_type(BCR, uint32_t,
__new_declare_io_value(BCR, uint32_t) {
struct SyncMode0 {
static constexpr auto NumberOfWords = BitRange::from_to(0, 15);
static constexpr auto CD_OneBlock = Bit(16);
static constexpr Self for_cd() {
// v Should be replaced with a named constant
return Self::from(SyncMode0::CD_OneBlock, SyncMode0::NumberOfWords.with(512));
static constexpr BCR for_cd() {
// v Should be replaced with a named constant
return BCR::from(SyncMode0::CD_OneBlock, SyncMode0::NumberOfWords.with(512));
}
};
@@ -25,10 +25,13 @@ namespace JabyEngine {
};
struct SyncMode2 {
static constexpr BCR for_gpu_cmd() {
return {0};
}
};
);
};
__declare_io_type(CHCHR, uint32_t,
__new_declare_io_value(CHCHR, uint32_t) {
enum SyncMode_t {
Sync0 = 0, //Start immediately,
Sync1 = 1, //Sync blocks to DMA requests
@@ -56,66 +59,57 @@ namespace JabyEngine {
static constexpr auto FromMainRAM = Bit(0);
static constexpr auto ToMainRAM = !FromMainRAM;
static constexpr Self StartMDECin() {
return Self{0x01000201};
static constexpr CHCHR StartMDECin() {
return CHCHR{0x01000201};
}
static constexpr Self StartMDECout() {
return Self{0x01000200};
static constexpr CHCHR StartMDECout() {
return CHCHR{0x01000200};
}
static constexpr Self StartGPUReceive() {
return Self{0x01000201};
static constexpr CHCHR StartGPUReceive() {
return CHCHR{0x01000201};
}
static constexpr Self StartGPULinked() {
return Self{0x01000401};
static constexpr CHCHR StartGPULinked() {
return CHCHR{0x01000401};
}
static constexpr Self StartCDROM() {
return Self{0x11000000};
static constexpr CHCHR StartCDROM() {
return CHCHR{0x11000000};
}
static constexpr Self StartSPUReceive() {
return Self{0x01000201};
static constexpr CHCHR StartSPUReceive() {
return CHCHR{0x01000201};
}
static constexpr Self StartOTC() {
return Self{0x11000002};
static constexpr CHCHR StartOTC() {
return CHCHR{0x11000002};
}
);
};
#pragma pack(push, 1)
struct Registers {
MADR_v adr;
BCR_v block_ctrl;
CHCHR_v channel_ctrl;
New::IOPort<MADR> adr;
New::IOPort<BCR> block_ctrl;
New::IOPort<CHCHR> channel_ctrl;
void set_adr(uintptr_t adr) {
this->adr.set(MADR_t::MemoryAdr.with(adr));
this->adr.write({bit::value::set_normalized(0u, MADR::MemoryAdr.with(adr))});
}
void wait() {
while(this->channel_ctrl.is_set(CHCHR_t::Busy));
while(this->channel_ctrl.read().is_set2(CHCHR::Busy));
}
};
#pragma pack(pop)
// Those types do not need to be volatile because there members are
typedef Registers MDECin_v;
typedef Registers MDECout_v;
typedef Registers GPU_v;
typedef Registers CDROM_v;
typedef Registers SPU_v;
typedef Registers PIO_v;
typedef Registers OTC_v;
//0: Highest, 7: Lowest
typedef uint32_t Priority;
static constexpr Priority HighestPriority = 0;
static constexpr Priority LowestPriority = 7;
__declare_io_type(DPCR, uint32_t,
__new_declare_io_value(DPCR, uint32_t) {
static constexpr auto OTCEnable = Bit(27);
static constexpr auto OTCPriority = BitRange::from_to(24, 26);
@@ -136,26 +130,26 @@ namespace JabyEngine {
static constexpr auto MDECinEnable = Bit(3);
static constexpr auto MDECinPriority = BitRange::from_to(0, 2);
);
};
__declare_io_type(DICR, uint32_t,
__new_declare_io_value(DICR, uint32_t) {
static constexpr auto MasterEnable = Bit(31);
static constexpr auto Flags = BitRange::from_to(24, 30);
static constexpr auto MasterEnableDPCR = Bit(23);
static constexpr auto EnableDPCR = BitRange::from_to(16, 22);
static constexpr auto ForceIRQ = Bit(15);
);
};
__declare_new_io_port(MDECin, 0x1F801080);
__declare_new_io_port(MDECout, 0x1F801090);
__declare_new_io_port(GPU, 0x1F8010A0);
__declare_new_io_port(CDROM, 0x1F8010B0);
__declare_new_io_port(SPU, 0x1F8010C0);
__declare_new_io_port(PIO, 0x1F8010D0);
__declare_new_io_port(OTC, 0x1F8010E0);
__new_declare_value_at(Registers, MDECin, 0x1F801080);
__new_declare_value_at(Registers, MDECout, 0x1F801090);
__new_declare_value_at(Registers, GPU, 0x1F8010A0);
__new_declare_value_at(Registers, CDROM, 0x1F8010B0);
__new_declare_value_at(Registers, SPU, 0x1F8010C0);
__new_declare_value_at(Registers, PIO, 0x1F8010D0);
__new_declare_value_at(Registers, OTC, 0x1F8010E0);
__declare_new_io_port(DPCR, 0x1F8010F0);
__declare_new_io_port(DICR, 0x1F8010F4);
__new_declare_io_port(DPCR, 0x1F8010F0);
__new_declare_io_port(DICR, 0x1F8010F4);
}
}
#endif //!__JABYENGINE_DMA_IO_HPP__