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Update IOPort code and prepare DMA usage - needs all testing

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jaby
2024-09-06 18:58:36 +01:00
parent a4426ad5d2
commit 97de034458
6 changed files with 14 additions and 41 deletions
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14
include/PSX/System/IOPorts/spu_io.hpp
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@@ -42,8 +42,6 @@ namespace JabyEngine {
return this->raw;
}
};
__declare_io_value(Adr, uint16_t) {
};
__declare_io_value(SampleRate, uint16_t) {
static constexpr SampleRate from_HZ(uint32_t freq) {
@@ -94,13 +92,13 @@ namespace JabyEngine {
IOPort<SweepVolume> volumeLeft; //Offset: 0x0
IOPort<SweepVolume> volumeRight; //Offset: 0x2
IOPort<SampleRate> sampleRate; //Offset: 0x4;
IOPort<Adr> adr; //Offset: 0x6
IOPort<SRAM_Adr> adr; //Offset: 0x6
IOPort<AD> ad; //Offset: 0x8
IOPort<SR> sr; //Offset: 0xA
IOPort<SimpleVolume> currentVolume; //Offset: 0xC
IOPort<Adr> repeatAdr; //Offset: 0xE
IOPort<SRAM_Adr> repeatAdr; //Offset: 0xE
static constexpr Adr start_adr() {
static constexpr SRAM_Adr start_adr() {
return {0x200};
}
};
@@ -147,16 +145,16 @@ namespace JabyEngine {
__declare_io_port_w_type(inline, SimpleVolume, Left, 0x1F801D84);
__declare_io_port_w_type(inline, SimpleVolume, Right, 0x1F801D86);
};
__declare_io_port_w_type(inline, Adr, WorkAreaAdr, 0x1F801DA2);
__declare_io_port_w_type(inline, SRAM_Adr, WorkAreaAdr, 0x1F801DA2);
};
static constexpr SimpleVolume operator""_vol(long double fraction) {
return {static_cast<int16_t>(static_cast<long double>(I16_MAX)*fraction)};
}
struct SRAMTransferAddressIO : public IOPortX<SRAM_Adr, SRAM_Adr> {};
struct SRAMTransferAddressIO : public IOPort<SRAM_Adr> {};
struct ControlRegisterIO : public IOPortX<SPU_IO_Values::ControlRegister> {
struct ControlRegisterIO : public IOPort<SPU_IO_Values::ControlRegister> {
using TransferMode = Value::RAMTransferMode;
void set_transfer_mode(TransferMode mode) {