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jaby
2024-09-06 18:32:09 +01:00
parent 0dcd2b71a6
commit a4426ad5d2
8 changed files with 143 additions and 32 deletions
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29
include/PSX/System/IOPorts/IOValues/spu_io_values.hpp Normal file
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@@ -0,0 +1,29 @@
#pragma once
#include "../ioport.hpp"
namespace JabyEngine {
namespace SPU_IO_Values {
__declare_io_value(ControlRegister, uint16_t) {
enum RAMTransferMode {
Stop = 0,
ManualWrite = 1,
DMAWrite = 2,
DMARead = 3
};
static constexpr auto Enable = Bit(15);
static constexpr auto Unmute = Bit(14);
static constexpr auto NoiseFrequcenyShift = BitRange::from_to(10, 13);
static constexpr auto NoiseFrequcenyStep = BitRange::from_to(8, 9);
static constexpr auto ReverbMasterEnable = Bit(7);
static constexpr auto IRQ9Enable = Bit(6);
static constexpr auto TransferMode = BitRange::from_to(4, 5);
static constexpr auto ExternalAudioReverb = Bit(3);
static constexpr auto CDAudioReverb = Bit(2);
static constexpr auto ExternalAudioEnable = Bit(1);
static constexpr auto CDAudioEnable = Bit(0);
};
using SRAM_Adr = uint16_t;
}
}

26
include/PSX/System/IOPorts/ioport.hpp
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@@ -74,8 +74,33 @@ namespace JabyEngine {
}
};
template<typename S, typename T = S::UnderlyingType>
struct IOPortX {
using Value = S;
S read() const {
return S{*const_cast<const volatile T*>(reinterpret_cast<const T*>(this))};
}
void write(S value) {
*const_cast<volatile T*>(reinterpret_cast<T*>(this)) = value.raw;
}
};
template<typename T>
struct IOPortX<T, T> {
T read() const {
return *const_cast<const volatile T*>(reinterpret_cast<const T*>(this));
}
void write(T value) {
*const_cast<volatile T*>(reinterpret_cast<T*>(this)) = value;
}
};
template<typename T>
struct IOPort {
using Value = T;
T value;
T read() const {
@@ -89,6 +114,7 @@ namespace JabyEngine {
template<>
struct IOPort<ubus32_t> {
using Value = ubus32_t;
ubus32_t value;
ubus32_t read() const {

45
include/PSX/System/IOPorts/spu_io.hpp
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@@ -1,9 +1,11 @@
#pragma once
#include "ioport.hpp"
#include "IOValues/spu_io_values.hpp"
#include <limits.hpp>
namespace JabyEngine {
namespace SPU_IO {
using namespace SPU_IO_Values;
namespace MemoryMap {
static constexpr uintptr_t ADPCM = 0x01000;
}
@@ -30,6 +32,9 @@ namespace JabyEngine {
typedef uint8_t Step;
__declare_io_value(DataTransferControl, uint16_t) {
static constexpr DataTransferControl NormalTransferMode() {
return DataTransferControl{0x0004};
}
};
__declare_io_value(SimpleVolume, int16_t) {
@@ -101,27 +106,6 @@ namespace JabyEngine {
};
#pragma pack(pop)
__declare_io_value(ControlRegister, uint16_t) {
enum RAMTransferMode {
Stop = 0,
ManualWrite = 1,
DMAWrite = 2,
DMARead = 3
};
static constexpr auto Enable = Bit(15);
static constexpr auto Unmute = Bit(14);
static constexpr auto NoiseFrequcenyShift = BitRange::from_to(10, 13);
static constexpr auto NoiseFrequcenyStep = BitRange::from_to(8, 9);
static constexpr auto ReverbMasterEnable = Bit(7);
static constexpr auto IRQ9Enable = Bit(6);
static constexpr auto TransferMode = BitRange::from_to(4, 5);
static constexpr auto ExternalAudioReverb = Bit(3);
static constexpr auto CDAudioReverb = Bit(2);
static constexpr auto ExternalAudioEnable = Bit(1);
static constexpr auto CDAudioEnable = Bit(0);
};
__declare_io_value(PMON, uint16_t) {
static constexpr auto EnableBits = BitRange::from_to(1, 23);
};
@@ -170,7 +154,22 @@ namespace JabyEngine {
return {static_cast<int16_t>(static_cast<long double>(I16_MAX)*fraction)};
}
__declare_io_port(, ControlRegister, 0x1F801DAA);
struct SRAMTransferAddressIO : public IOPortX<SRAM_Adr, SRAM_Adr> {};
struct ControlRegisterIO : public IOPortX<SPU_IO_Values::ControlRegister> {
using TransferMode = Value::RAMTransferMode;
void set_transfer_mode(TransferMode mode) {
this->write(this->read().set(ControlRegister::TransferMode.with(mode)));
while(this->read().get(ControlRegister::TransferMode) != mode);
}
};
// TODO: The new way? v Parse with a Macro?
static auto& ControlRegister = *reinterpret_cast<ControlRegisterIO*>(0x1F801DAA);
static auto& SRAMTransferAdr = *reinterpret_cast<SRAMTransferAddressIO*>(0x1F801DA6);
//__declare_io_port(, ControlRegister, 0x1F801DAA);
__declare_io_port(, DataTransferControl, 0x1F801DAC);
__declare_io_port(, PMON, 0x1F801D90);
__declare_io_port(, NON, 0x1F801D94);