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Use new IO Port related types and further improvements of readability #1

Merged
jaby merged 18 commits from Overlay-The-Beginning_CDDrive_EndOfIO into Overlay-The-Beginning_CDDrive 2023-03-23 19:43:52 +00:00
Conversation 0 Commits 18 Files Changed 25 +92 -74
4 changed files with 92 additions and 74 deletions
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151
include/PSX/System/IOPorts/dma_io.hpp
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@ -4,130 +4,147 @@
namespace JabyEngine {
namespace DMA_IO {
struct MADR : public ComplexBitMap<uint32_t> {
static constexpr auto MemoryAdr = BitRange<uint32_t>::from_to(0, 23);
};
__declare_io_type(MADR, uint32_t,
static constexpr auto MemoryAdr = IOValueSet::from_to(0, 23);
);
struct BCR : public ComplexBitMap<uint32_t> {
__declare_io_type(BCR, uint32_t,
struct __no_align SyncMode0 {
static constexpr auto NumberOfWords = BitRange<uint16_t>::from_to(0, 15);
static constexpr auto CD_OneBlock = Bit<uint16_t>(16);
static constexpr auto NumberOfWords = IOValueSet::from_to(0, 15);
static constexpr auto CD_OneBlock = IOBitSet(16);
};
struct SyncMode1 : public ComplexBitMap<uint32_t> {
static constexpr auto BlockSize = BitRange<uint32_t>::from_to(0, 15);
static constexpr auto BlockAmount = BitRange<uint32_t>::from_to(16, 31);
static constexpr auto BlockSize = IOValueSet::from_to(0, 15);
static constexpr auto BlockAmount = IOValueSet::from_to(16, 31);
};
struct SyncMode2 {
};
};
);
struct CHCHR : public ComplexBitMap<uint32_t> {
enum _SyncMode {
__declare_io_type(CHCHR, uint32_t,
enum SyncMode_t {
Sync0 = 0, //Start immediately,
Sync1 = 1, //Sync blocks to DMA requests
Sync2 = 2, //Linked List
};
static constexpr auto ManualStart = Bit<uint32_t>(28);
static constexpr auto ManualStart = IOBitSet(28);
static constexpr auto Start = Bit<uint32_t>(24);
static constexpr auto Start = IOBitSet(24);
static constexpr auto Busy = Start;
static constexpr auto ChoppingCPUWindowSize = BitRange<uint32_t>::from_to(20, 22);
static constexpr auto ChoppingDMAWindowSize = BitRange<uint32_t>::from_to(16, 18);
static constexpr auto ChoppingCPUWindowSize = IOValueSet::from_to(20, 22);
static constexpr auto ChoppingDMAWindowSize = IOValueSet::from_to(16, 18);
static constexpr auto SyncMode = BitRange<_SyncMode>::from_to(9, 10);
static constexpr auto SyncMode = IOValueSet::from_to(9, 10);
static constexpr auto UseSyncMode0 = SyncMode.with(Sync0);
static constexpr auto UseSyncMode1 = SyncMode.with(Sync1);
static constexpr auto UseSyncMode2 = SyncMode.with(Sync2);
static constexpr auto UseChopping = Bit<uint32_t>(8);
static constexpr auto UseChopping = IOBitSet(8);
static constexpr auto MemoryAdrDecreaseBy4 = Bit<uint32_t>(1);
static constexpr auto MemoryAdrDecreaseBy4 = IOBitSet(1);
static constexpr auto MemoryAdrIncreaseBy4 = !MemoryAdrDecreaseBy4;
static constexpr auto FromMainRAM = Bit<uint32_t>(0);
static constexpr auto FromMainRAM = IOBitSet(0);
static constexpr auto ToMainRAM = !FromMainRAM;
static constexpr CHCHR StartMDECin() {
return CHCHR{0x01000201};
static constexpr Self StartMDECin() {
return Self{0x01000201};
}
static constexpr CHCHR StartMDECout() {
return CHCHR{0x01000200};
static constexpr Self StartMDECout() {
return Self{0x01000200};
}
static constexpr CHCHR StartGPUReceive() {
return CHCHR{0x01000201};
static constexpr Self StartGPUReceive() {
return Self{0x01000201};
}
static constexpr CHCHR StartCDROM() {
return CHCHR{0x11000000};
static constexpr Self StartCDROM() {
return Self{0x11000000};
}
static constexpr CHCHR StartSPUReceive() {
return CHCHR{0x01000201};
static constexpr Self StartSPUReceive() {
return Self{0x01000201};
}
static constexpr CHCHR StartOTC() {
return CHCHR{0x11000002};
static constexpr Self StartOTC() {
return Self{0x11000002};
}
};
);
struct __no_align Registers {
VolatileBitMapPOD<MADR> adr;
VolatileBitMapPOD<BCR> block_ctrl;
VolatileBitMapPOD<CHCHR> channel_ctrl;
MADR_v adr;
BCR_v block_ctrl;
CHCHR_v channel_ctrl;
void set_adr(uintptr_t adr) {
this->adr.set(MADR_t::MemoryAdr.with(adr));
}
void wait() {
while(this->channel_ctrl.is_set(CHCHR_t::Busy));
}
};
// Those types do not need to be volatile because there members are
typedef Registers MDECin_v;
typedef Registers MDECout_v;
typedef Registers GPU_v;
typedef Registers CDROM_v;
typedef Registers SPU_v;
typedef Registers PIO_v;
typedef Registers OTC_v;
//0: Highest, 7: Lowest
typedef uint32_t Priority;
static constexpr Priority HighestPriority = 0;
static constexpr Priority LowestPriority = 7;
struct DMAControlRegister : public ComplexBitMap<uint32_t> {
static constexpr auto OTCEnable = Bit<uint32_t>(27);
static constexpr auto OTCPriority = BitRange<Priority>::from_to(24, 26);
__declare_io_type(DPCR, uint32_t,
static constexpr auto OTCEnable = IOBitSet(27);
static constexpr auto OTCPriority = IOValueSet::from_to(24, 26);
static constexpr auto PIOEnable = Bit<uint32_t>(23);
static constexpr auto PIOPriority = BitRange<Priority>::from_to(20, 22);
static constexpr auto PIOEnable = IOBitSet(23);
static constexpr auto PIOPriority = IOValueSet::from_to(20, 22);
static constexpr auto SPUEnable = Bit<uint32_t>(19);
static constexpr auto SPUPriority = BitRange<Priority>::from_to(16, 18);
static constexpr auto SPUEnable = IOBitSet(19);
static constexpr auto SPUPriority = IOValueSet::from_to(16, 18);
static constexpr auto CDROMEnable = Bit<uint32_t>(15);
static constexpr auto CDROMPriority = BitRange<Priority>::from_to(12, 14);
static constexpr auto CDROMEnable = IOBitSet(15);
static constexpr auto CDROMPriority = IOValueSet::from_to(12, 14);
static constexpr auto GPUEnable = Bit<uint32_t>(11);
static constexpr auto GPUPriority = BitRange<Priority>::from_to(8, 10);
static constexpr auto GPUEnable = IOBitSet(11);
static constexpr auto GPUPriority = IOValueSet::from_to(8, 10);
static constexpr auto MDECoutEnable = Bit<uint32_t>(7);
static constexpr auto MDECoutPriority = BitRange<Priority>::from_to(4, 6);
static constexpr auto MDECoutEnable = IOBitSet(7);
static constexpr auto MDECoutPriority = IOValueSet::from_to(4, 6);
static constexpr auto MDECinEnable = Bit<uint32_t>(3);
static constexpr auto MDECinPriority = BitRange<Priority>::from_to(0, 2);
};
static constexpr auto MDECinEnable = IOBitSet(3);
static constexpr auto MDECinPriority = IOValueSet::from_to(0, 2);
);
struct DMAInterruptRegister : public ComplexBitMap<uint32_t> {
static constexpr auto MasterEnable = Bit<uint32_t>(31);
static constexpr auto Flags = BitRange<uint32_t>::from_to(24, 30);
static constexpr auto MasterEnableDPCR = Bit<uint32_t>(23);
static constexpr auto EnableDPCR = BitRange<uint32_t>::from_to(16, 22);
static constexpr auto ForceIRQ = Bit<uint32_t>(15);
};
__declare_io_type(DICR, uint32_t,
static constexpr auto MasterEnable = IOBitSet(31);
static constexpr auto Flags = IOValueSet::from_to(24, 30);
static constexpr auto MasterEnableDPCR = IOBitSet(23);
static constexpr auto EnableDPCR = IOValueSet::from_to(16, 22);
static constexpr auto ForceIRQ = IOBitSet(15);
);
__declare_io_port_global_struct(Registers, MDECin, 0x1F801080);
__declare_io_port_global_struct(Registers, MDECout, 0x1F801090);
__declare_io_port_global_struct(Registers, GPU, 0x1F8010A0);
__declare_io_port_global_struct(Registers, CDROM, 0x1F8010B0);
__declare_io_port_global_struct(Registers, SPU, 0x1F8010C0);
__declare_io_port_global_struct(Registers, PIO, 0x1F8010D0);
__declare_io_port_global_struct(Registers, OTC, 0x1F8010E0);
__declare_new_io_port(MDECin, 0x1F801080);
__declare_new_io_port(MDECout, 0x1F801090);
__declare_new_io_port(GPU, 0x1F8010A0);
__declare_new_io_port(CDROM, 0x1F8010B0);
__declare_new_io_port(SPU, 0x1F8010C0);
__declare_new_io_port(PIO, 0x1F8010D0);
__declare_new_io_port(OTC, 0x1F8010E0);
__declare_io_port_global(DMAControlRegister, DPCR, 0x1F8010F0);
__declare_io_port_global(DMAInterruptRegister, DICR, 0x1F8010F4);
__declare_new_io_port(DPCR, 0x1F8010F0);
__declare_new_io_port(DICR, 0x1F8010F4);
}
}
#endif //!__JABYENGINE_DMA_IO_HPP__

1
include/PSX/System/IOPorts/ioport.hpp
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@ -75,7 +75,6 @@ namespace JabyEngine {
static constexpr name##_io_base from(const ARGS&...args) { \
return name##_io_base().set_va(args...); \
} \
\
constexpr name##_io_base& set(IOBitSet bit) { \
this->raw_value = bit::set(this->raw_value, bit.pos); \
return *this; \

10
src/Library/include/GPU/gpu_internal.hpp
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@ -48,7 +48,7 @@ namespace JabyEngine {
namespace DMA {
static void wait() {
while(::JabyEngine::DMA_IO::GPU.channel_ctrl.read().is(::JabyEngine::DMA_IO::CHCHR::Busy));
::JabyEngine::DMA_IO::GPU.wait();
}
static void end() {
@ -62,7 +62,7 @@ namespace JabyEngine {
}
static void set_src(uintptr_t adr) {
DMA_IO::GPU.adr.write(DMA_IO::MADR::MemoryAdr.with(static_cast<uint32_t>(adr)));
DMA_IO::GPU.set_adr(adr);
}
static void set_dst(const PositionU16& position, const SizeU16& size) {
@ -73,10 +73,10 @@ namespace JabyEngine {
}
static void start(uint16_t blockCount, uint16_t wordsPerBlock = 0x10) {
typedef DMA_IO::BCR::SyncMode1 SyncMode1;
typedef DMA_IO::BCR_t::SyncMode1 SyncMode1;
DMA_IO::GPU.block_ctrl.write(DMA_IO::BCR{SyncMode1::with(SyncMode1::BlockSize.with(wordsPerBlock), SyncMode1::BlockAmount.with(blockCount))});
DMA_IO::GPU.channel_ctrl.write(DMA_IO::CHCHR::StartGPUReceive());
DMA_IO::GPU.block_ctrl = *DMA_IO::BCR_t::from(SyncMode1::BlockSize.with(wordsPerBlock), SyncMode1::BlockAmount.with(blockCount));
DMA_IO::GPU.channel_ctrl = *DMA_IO::CHCHR_t::StartGPUReceive();
}
}
}

4
src/Library/src/BootLoader/start_boot.cpp
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@ -1,6 +1,7 @@
#include "BootLoader/boot_loader.hpp"
#include <PSX/System/IOPorts/dMa_io.hpp>
// 2x For setup timing
#include <PSX/Timer/high_res_timer.hpp>
#include <stdio.h>
@ -8,7 +9,8 @@ namespace JabyEngine {
namespace boot {
namespace Start {
static void enable_DMA() {
DMA_IO::DPCR.write(DMA_IO::DMAControlRegister{DMA_IO::DPCR.read() | DMA_IO::DMAControlRegister::SPUEnable | DMA_IO::DMAControlRegister::GPUEnable});
const auto dpcr = DMA_IO::DPCR_t(*DMA_IO::DPCR).set(DMA_IO::DPCR_t::SPUEnable).set(DMA_IO::DPCR_t::GPUEnable);
DMA_IO::DPCR = *dpcr;
}
JabyEngine::NextRoutine setup() {