181 lines
6.7 KiB
C++
181 lines
6.7 KiB
C++
#pragma once
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#include "ioport.hpp"
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namespace JabyEngine {
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namespace DMA_IO {
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__declare_io_value(MADR, uint32_t) {
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static constexpr auto MemoryAdr = BitRange::from_to(0, 23);
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};
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__declare_io_value(BCR, uint32_t) {
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struct SyncMode0 {
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static constexpr auto NumberOfWords = BitRange::from_to(0, 15);
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static constexpr auto CD_OneBlock = Bit(16);
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static constexpr BCR for_cd() {
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// v Should be replaced with a named constant
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return BCR::from(SyncMode0::CD_OneBlock, SyncMode0::NumberOfWords.with(512));
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}
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};
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struct SyncMode1 {
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static constexpr auto BlockSize = BitRange::from_to(0, 15);
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static constexpr auto BlockAmount = BitRange::from_to(16, 31);
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};
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struct SyncMode2 {
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static constexpr BCR for_gpu_cmd() {
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return {0};
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}
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};
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};
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__declare_io_value(CHCHR, uint32_t) {
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enum SyncMode_t {
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Sync0 = 0, //Start immediately,
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Sync1 = 1, //Sync blocks to DMA requests
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Sync2 = 2, //Linked List
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};
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static constexpr auto ManualStart = Bit(28);
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static constexpr auto Start = Bit(24);
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static constexpr auto Busy = Start;
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static constexpr auto ChoppingCPUWindowSize = BitRange::from_to(20, 22);
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static constexpr auto ChoppingDMAWindowSize = BitRange::from_to(16, 18);
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static constexpr auto SyncMode = BitRange::from_to(9, 10);
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static constexpr auto UseSyncMode0 = SyncMode.with(Sync0);
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static constexpr auto UseSyncMode1 = SyncMode.with(Sync1);
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static constexpr auto UseSyncMode2 = SyncMode.with(Sync2);
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static constexpr auto UseChopping = Bit(8);
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static constexpr auto MemoryAdrDecreaseBy4 = Bit(1);
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static constexpr auto MemoryAdrIncreaseBy4 = !MemoryAdrDecreaseBy4;
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static constexpr auto FromMainRAM = Bit(0);
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static constexpr auto ToMainRAM = !FromMainRAM;
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static constexpr CHCHR StartMDECin() {
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return CHCHR{0x01000201};
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}
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static constexpr CHCHR StartMDECout() {
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return CHCHR{0x01000200};
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}
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static constexpr CHCHR StartGPUReceive() {
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return CHCHR{0x01000201};
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}
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static constexpr CHCHR StartGPULinked() {
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return CHCHR{0x01000401};
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}
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static constexpr CHCHR StartCDROM() {
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return CHCHR{0x11000000};
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}
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static constexpr CHCHR StartSPUReceive() {
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return CHCHR{0x01000201};
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}
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static constexpr CHCHR StartOTC() {
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return CHCHR{0x11000002};
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}
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};
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#pragma pack(push, 1)
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struct Registers {
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IOPort<MADR> adr;
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IOPort<BCR> block_ctrl;
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IOPort<CHCHR> channel_ctrl;
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inline void set_adr(uintptr_t adr) {
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this->adr.write({bit::value::set_normalized(0u, MADR::MemoryAdr.with(adr))});
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}
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inline void wait() {
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while(this->channel_ctrl.read().is_set(CHCHR::Busy));
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}
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};
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#pragma pack(pop)
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//0: Highest, 7: Lowest
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typedef uint32_t Priority;
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static constexpr Priority HighestPriority = 0;
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static constexpr Priority LowestPriority = 7;
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__declare_io_value(DPCR, uint32_t) {
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struct DMASetting {
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uint16_t master_bit;
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static constexpr DMASetting create(uint16_t master_bit) {
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return DMASetting{master_bit};
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}
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constexpr BitRange::RangeValuePair<uint32_t> turn_on(uint8_t priority) const {
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return BitRange::from_to(this->master_bit - 3, this->master_bit).with(static_cast<uint32_t>(0b1000 + (priority & 0b111)));
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}
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constexpr ClearBit turn_off() const {
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return ClearBit(this->master_bit);
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}
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};
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static constexpr const auto OTC = DMASetting(27);
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static constexpr const auto PIO = DMASetting(23);
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static constexpr const auto SPU = DMASetting(19);
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static constexpr const auto CDROM = DMASetting(15);
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static constexpr const auto GPU = DMASetting(11);
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static constexpr const auto MDEC_Out = DMASetting(7);
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static constexpr const auto MDEC_In = DMASetting(3);
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static constexpr auto OTCEnabled = Bit(27);
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static constexpr auto OTCPriority = BitRange::from_to(24, 26);
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static constexpr auto PIOEnabled = Bit(23);
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static constexpr auto PIOPriority = BitRange::from_to(20, 22);
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static constexpr auto SPUEnabled = Bit(19);
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static constexpr auto SPUPriority = BitRange::from_to(16, 18);
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static constexpr auto CDROMEnabled = Bit(15);
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static constexpr auto CDROMPriority = BitRange::from_to(12, 14);
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static constexpr auto GPUEnabled = Bit(11);
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static constexpr auto GPUPriority = BitRange::from_to(8, 10);
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static constexpr auto MDECoutEnabled = Bit(7);
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static constexpr auto MDECoutPriority = BitRange::from_to(4, 6);
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static constexpr auto MDECinEnabled = Bit(3);
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static constexpr auto MDECinPriority = BitRange::from_to(0, 2);
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};
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__declare_io_value(DICR, uint32_t) {
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static constexpr auto MasterEnable = Bit(31);
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static constexpr auto Flags = BitRange::from_to(24, 30);
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static constexpr auto MasterEnableDPCR = Bit(23);
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static constexpr auto EnableDPCR = BitRange::from_to(16, 22);
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static constexpr auto ForceIRQ = Bit(15);
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static constexpr DICR empty() {
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return DICR{0};
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}
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};
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__declare_value_at(, Registers, MDECin, 0x1F801080);
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__declare_value_at(, Registers, MDECout, 0x1F801090);
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__declare_value_at(, Registers, GPU, 0x1F8010A0);
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__declare_value_at(, Registers, CDROM, 0x1F8010B0);
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__declare_value_at(, Registers, SPU, 0x1F8010C0);
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__declare_value_at(, Registers, PIO, 0x1F8010D0);
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__declare_value_at(, Registers, OTC, 0x1F8010E0);
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__declare_io_port(, DPCR, 0x1F8010F0);
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__declare_io_port(, DICR, 0x1F8010F4);
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}
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} |