114 lines
4.5 KiB
C++
114 lines
4.5 KiB
C++
#pragma once
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#include <PSX/GPU/gpu.hpp>
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#include <PSX/System/IOPorts/dma_io.hpp>
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#include <PSX/System/IOPorts/gpu_io.hpp>
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namespace JabyEngine {
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namespace GPU {
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namespace internal {
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struct Display {
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typedef ::JabyEngine::GPU::Display PublicDisplay;
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static constexpr auto Width = PublicDisplay::Width;
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static constexpr auto Height = PublicDisplay::Height;
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#ifdef JABYENGINE_PAL
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static constexpr auto DisplayMode = GPU_IO_Values::DisplayMode::PAL();
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static constexpr uint16_t ScanlinesV = 288;
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static constexpr auto DisplayRange = PositionI16::create(78, 35);
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#else
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static constexpr auto DisplayMode = GPU_IO_Values::DisplayMode::NTSC();
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static constexpr uint16_t ScanlinesV = 240;
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static constexpr auto DisplayRange = PositionI16::create(76, 16);
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#endif //JABYENGINE_PAL
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static uint32_t exchange_buffer_and_display();
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};
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void wait_vsync(uint8_t syncs);
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static void wait_ready_for_CMD() {
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GPU::wait_for_render();
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}
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static void set_draw_area(const PositionU16& pos) {
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wait_ready_for_CMD();
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GPU_IO::GP0.set_draw_area_top_left(pos);
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wait_ready_for_CMD();
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GPU_IO::GP0.set_draw_area_bottom_right(pos.move((Display::Width - 1), (Display::Height - 1)));
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}
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static void copy_vram_to_vram(const AreaU16& dst, const PositionU16& src) {
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wait_ready_for_CMD();
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GPU_IO::GP0.set_vram2vram_blitting();
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GPU_IO::GP0.pass_top_left_position(src);
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GPU_IO::GP0.pass_top_left_position(dst.position);
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GPU_IO::GP0.pass_width_height(dst.size);
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}
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static void quick_fill_fast(const Color24& color, const AreaU16& area) {
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wait_ready_for_CMD();
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GPU_IO::GP0.quick_fill(color);
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GPU_IO::GP0.pass_top_left_position(area.position);
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GPU_IO::GP0.pass_width_height(area.size);
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}
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static void set_draw_offset(const PositionI16& offset) {
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wait_ready_for_CMD();
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GPU_IO::GP0.set_draw_offset(offset);
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}
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static void reset_cmd_buffer() {
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GPU_IO::GP1.reset_cmd_buffer();
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}
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struct DMA {
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#ifdef __SUPPORT_PS3__
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// The PS3 doesn't autoincrement the GPU MADR register so we have to do it
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static uintptr_t MADR;
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#endif // __SUPPORT_PS3__
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static void wait() {
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DMA_IO::GPU.wait();
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}
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static void end() {
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reset_cmd_buffer();
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}
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struct Receive {
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static void prepare() {
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GPU_IO::GP1.set_dma_direction(GPU_IO_Values::GPUSTAT::DMADirection::CPU2GPU);
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reset_cmd_buffer();
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}
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static void set_src(uintptr_t adr) {
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#ifdef __SUPPORT_PS3__
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DMA::MADR = adr;
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#else
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DMA_IO::GPU.set_adr(adr);
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#endif // __SUPPORT_PS3__
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}
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static void set_dst(const PositionU16& position, const SizeU16& size) {
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wait_ready_for_CMD();
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GPU_IO::GP0.set_cpu2vram_blitting();
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GPU_IO::GP0.pass_top_left_position(position);
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GPU_IO::GP0.pass_width_height(size);
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}
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static void start(uint16_t blockCount, uint16_t wordsPerBlock = 0x10) {
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using SyncMode1 = DMA_IO::BCR::SyncMode1;
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#ifdef __SUPPORT_PS3__
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DMA_IO::GPU.set_adr(MADR);
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DMA::MADR += (blockCount * wordsPerBlock) << 2;
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#endif // __SUPPORT_PS3__
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DMA_IO::GPU.block_ctrl.write(DMA_IO::BCR::from(SyncMode1::BlockSize.with(wordsPerBlock), SyncMode1::BlockAmount.with(blockCount)));
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DMA_IO::GPU.channel_ctrl.write(DMA_IO::CHCHR::StartGPUReceive());
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}
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};
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};
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}
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}
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} |