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Move gte_instructions back

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jaby
2024-01-28 22:15:21 -05:00
parent 6f48d1ff6c
commit 493a33cff9
4 changed files with 109 additions and 93 deletions
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28
src/Library/src/GTE/gte.cpp
View File

@@ -1,13 +1,12 @@
#include "gte_instruction.hpp"
#include <PSX/GTE/gte.hpp>
namespace JabyEngine {
namespace GTE {
void rot_trans(const SVECTOR& input, VECTOR& output, int32_t& flag) {
ldv0(input);
rt();
stlvnl(output);
stflg(flag);
__jaby_engine_gte_ldv0(input);
__jaby_engine_gte_rt();
__jaby_engine_gte_stlvnl(output);
__jaby_engine_gte_stflg(flag);
}
void set_rot_matrix(const MATRIX& matrix) {
@@ -35,21 +34,22 @@ namespace JabyEngine {
MATRIX& mult_matrix(const MATRIX& m0, const MATRIX& m1, MATRIX& result) {
/*
Jaby: Somehow this code creates stack usage.... Investigate!!
Jaby: Reimplement all of this with the original code and see how it goes?!
*/
asm("# MY PLANSCHI START");
set_rot_matrix(m0);
ldclmv(m1, 0);
rtir();
stclmv(result, 0);
__jaby_engine_gte_ldclmv(m1, 0);
__jaby_engine_gte_rtir();
__jaby_engine_gte_stclmv(result, 0);
ldclmv(m1, 1);
rtir();
stclmv(result, 1);
__jaby_engine_gte_ldclmv(m1, 1);
__jaby_engine_gte_rtir();
__jaby_engine_gte_stclmv(result, 1);
ldclmv(m1, 2);
rtir();
stclmv(result, 2);
__jaby_engine_gte_ldclmv(m1, 2);
__jaby_engine_gte_rtir();
__jaby_engine_gte_stclmv(result, 2);
return result;
asm("# MY PLANSCHI END");

78
src/Library/src/GTE/gte_instruction.hpp
View File

@@ -1,78 +0,0 @@
#pragma once
#include <PSX/GTE/gte_types.hpp>
namespace JabyEngine {
namespace GTE {
// Load vertex or normal to vertex register 0
static __always_inline void ldv0(const SVECTOR& vector) {
__asm__ volatile("lwc2 $0, 0(%0)" :: "r"(&vector));
__asm__ volatile("lwc2 $1, 4(%0)" :: "r"(&vector));
}
// Load vertex or normal to vertex register 1
static __always_inline void ldv1(const SVECTOR& vector) {
__asm__ volatile("lwc2 $2, 0(%0)" :: "r"(&vector));
__asm__ volatile("lwc2 $3, 4(%0)" :: "r"(&vector));
}
// Load vertex or normal to vertex register 2
static __always_inline void ldv2(const SVECTOR& vector) {
__asm__ volatile("lwc2 $4, 0(%0)" :: "r"(&vector));
__asm__ volatile("lwc2 $5, 4(%0)" :: "r"(&vector));
}
// Load column vector of MATRIX to universal register
static __always_inline void ldclmv(const MATRIX& matrix, size_t col) {
__asm__ volatile("lhu $12, 0(%0)" :: "r"(reinterpret_cast<uintptr_t>(&matrix) + (col << 1)) : "$12", "$13", "$14");
__asm__ volatile("lhu $13, 6(%0)" :: "r"(reinterpret_cast<uintptr_t>(&matrix) + (col << 1)) : "$12", "$13", "$14");
__asm__ volatile("lhu $14, 12(%0)" :: "r"(reinterpret_cast<uintptr_t>(&matrix) + (col << 1)) : "$12", "$13", "$14");
__asm__ volatile("mtc2 $12, $9" :: "r"(reinterpret_cast<uintptr_t>(&matrix) + (col << 1)) : "$12", "$13", "$14");
__asm__ volatile("mtc2 $13, $10" :: "r"(reinterpret_cast<uintptr_t>(&matrix) + (col << 1)) : "$12", "$13", "$14");
__asm__ volatile("mtc2 $14, $11" :: "r"(reinterpret_cast<uintptr_t>(&matrix) + (col << 1)) : "$12", "$13", "$14");
}
// Store flag
static __always_inline void stflg(int32_t& flag) {
__asm__ volatile("cfc2 $12, $31" :: "r"(&flag) : "$12", "memory");
__asm__ volatile("nop" :: "r"(&flag) : "$12", "memory");
__asm__ volatile("sw $12, 0(%0)" :: "r"(&flag) : "$12", "memory");
}
// Store MATRIX column from 16 bit universal register
static __always_inline void stclmv(MATRIX& matrix, size_t col) {
__asm__ volatile("mfc2 $12, $9" :: "r"(reinterpret_cast<uintptr_t>(&matrix) + (col << 1)) : "$12", "$13", "$14", "memory");
__asm__ volatile("mfc2 $13, $10" :: "r"(reinterpret_cast<uintptr_t>(&matrix) + (col << 1)) : "$12", "$13", "$14", "memory");
__asm__ volatile("mfc2 $14, $11" :: "r"(reinterpret_cast<uintptr_t>(&matrix) + (col << 1)) : "$12", "$13", "$14", "memory");
__asm__ volatile("sh $12, 0(%0)" :: "r"(reinterpret_cast<uintptr_t>(&matrix) + (col << 1)) : "$12", "$13", "$14", "memory");
__asm__ volatile("sh $13, 6(%0)" :: "r"(reinterpret_cast<uintptr_t>(&matrix) + (col << 1)) : "$12", "$13", "$14", "memory");
__asm__ volatile("sh $14, 12(%0)" :: "r"(reinterpret_cast<uintptr_t>(&matrix) + (col << 1)) : "$12", "$13", "$14", "memory");
}
// Store VECTOR from 32 bit universal register
static __always_inline void stlvnl(VECTOR& out_vector) {
__asm__ volatile("swc2 $25, 0(%0)" :: "r"(&out_vector) : "memory");
__asm__ volatile("swc2 $26, 4(%0)" :: "r"(&out_vector) : "memory");
__asm__ volatile("swc2 $27, 8(%0)" :: "r"(&out_vector) : "memory");
}
/*
Kernel of RotTrans
(Transfer vector)+(Rotation Matrix)*(vertex register 0)
*/
static __always_inline void rt() {
__asm__ volatile("nop");
__asm__ volatile("nop");
__asm__ volatile("cop2 0x0480012");
}
/*
Variation of gte_rt
(Rotation Matrix)*(16 bit universal vector)
*/
static __always_inline void rtir() {
__asm__ volatile("nop");
__asm__ volatile("nop");
__asm__ volatile("cop2 0x049E012");
}
}
}